Harold W. Cain
According to our database1, Harold W. Cain authored at least 23 papers between 2000 and 2018.
Legend:Book In proceedings Article PhD thesis Other
SPF: Selective Pipeline Flush.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Load value prediction via path-based address prediction: avoiding mispredictions due to conflicting stores.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
PABST: Proportionally Allocated Bandwidth at the Source and Target.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
Robust architectural support for transactional memory in the power architecture.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013
RECAP: A region-based cure for the common cold (cache).
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
Edge chasing delayed consistency: pushing the limits of weak memory models.
Proceedings of the 2012 ACM workshop on Relaxing synchronization for multicore and manycore scalability, 2012
Cache restoration for highly partitioned virtualized systems.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012
ReCaP: a region-based cure for the common cold cache.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012
Runahead execution vs. conventional data prefetching in the IBM POWER6 microprocessor.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2010
Compiler and runtime techniques for software transactional memory optimization.
Concurrency and Computation: Practice and Experience, 2009
Software transactional memory: why is it only a research toy?
Commun. ACM, 2008
Call-chain Software Instruction Prefetching in J2EE Server Applications.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007
Accurate, efficient, and adaptive calling context profiling.
Proceedings of the ACM SIGPLAN 2006 Conference on Programming Language Design and Implementation, 2006
Conditional Memory Ordering.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006
Memory Ordering: A Value-Based Approach.
IEEE Micro, 2004
Constraint Graph Analysis of Multithreaded Programs.
J. Instruction-Level Parallelism, 2004
Redeeming IPC as a Performance Metric for Multithreaded Programs.
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September, 2003
A callgraph-based search strategy for automated performance diagnosis.
Concurrency and Computation: Practice and Experience, 2002
Verifying sequential consistency using vector clocks.
Proceedings of the Fourteenth Annual ACM Symposium on Parallel Algorithms and Architectures, 2002
A dynamic binary translation approach to architectural simulation.
SIGARCH Computer Architecture News, 2001
Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001
An Architectural Evaluation of Java TPC-W.
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001
A Callgraph-Based Search Strategy for Automated Performance Diagnosis (Distinguished Paper).
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000