Moriyoshi Ohara

According to our database1, Moriyoshi Ohara authored at least 27 papers between 1991 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Automatic Optimize-time Validation for Binary Optimizers.
J. Inf. Process., 2022

Detecting Layered Bottlenecks in Microservices.
Proceedings of the IEEE 15th International Conference on Cloud Computing, 2022

2021

2020
Efficient AI System Design With Cross-Layer Approximate Computing.
Proc. IEEE, 2020

Hyperledger Fabric Performance Characterization and Optimization Using GoLevelDB Benchmark.
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2020

2019
DeepTools: Compiler and Execution Runtime Extensions for RaPiD AI Accelerator.
IEEE Micro, 2019

Profile-based Detection of Layered Bottlenecks.
Proceedings of the 2019 ACM/SPEC International Conference on Performance Engineering, 2019

A Compiler for Deep Neural Network Accelerators to Generate Optimized Code for a Wide Range of Data Parameters from a Hand-crafted Computation Kernel.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2019

2017
Identifying the potential of near data processing for apache spark.
Proceedings of the International Symposium on Memory Systems, 2017

Performance competitiveness of a statically compiled language for server-side Web applications.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

Accelerating Spark Datasets by Inlining Deserialization.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

2016
Workload characterization for microservices.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

Container management as emerging workload for operating systems.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

A power-efficient FPGA accelerator: Systolic array with cache-coherent interface for pair-HMM algorithm.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016

Re-constructing high-level information for language-specific binary re-optimization.
Proceedings of the 2016 International Symposium on Code Generation and Optimization, 2016

2014
Faster Set Intersection with SIMD instructions by Reducing Branch Mispredictions.
Proc. VLDB Endow., 2014

Characterization of call-graph profiles in Java workloads.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014

2013
Scaling analytics applications with OpenCL for loosely coupled heterogeneous clusters.
Proceedings of the Computing Frontiers Conference, 2013

2012
Optimizing indirect branches in a system-level dynamic binary translator.
Proceedings of the 5th Annual International Systems and Storage Conference, 2012

2010
Aggregating REST requests to accelerate Web 2.0 applications.
IBM J. Res. Dev., 2010

2009
The data-centricity of Web 2.0 workloads and its impact on server performance.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009

2007
Real-Time Mutual-Information-Based Linear Registration on the Cell Broadband Engine Processor.
Proceedings of the 2007 IEEE International Symposium on Biomedical Imaging: From Nano to Macro, 2007

Accelerating Mutual-Information-Based Linear Registration on the Cell Broadband Engine Processor.
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007

2006
MPI microtask for programming the Cell Broadband Engine<sup>TM</sup> processor.
IBM Syst. J., 2006

1998
The Design of COMPASS: An Execution Driven Simulator for Commercial Applications Running on Shared Memory Multiprocessors.
Proceedings of the 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30, 1998

1995
The SPLASH-2 Programs: Characterization and Methodological Considerations.
Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

1991
Design choices for the TOP-1 multiprocessor workstation.
IBM J. Res. Dev., 1991


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