Tao Jiang

Affiliations:
  • Qualcomm, San Diego, CA, USA
  • Orgeon State University, Corvallis, OR, USA


According to our database1, Tao Jiang authored at least 8 papers between 2009 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2012
A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS.
IEEE J. Solid State Circuits, 2012

0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking.
IEEE J. Solid State Circuits, 2012

A low-power, capacitively-divided, ring oscillator with digitally adjustable voltage swing.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

2011
Low-power 8Gb/s near-threshold serial link receivers using super-harmonic injection locking in 65nm CMOS.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
A 0.6 mW/Gb/s, 6.4-7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS.
IEEE J. Solid State Circuits, 2010

Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR-ADC in 40nm-CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Sense Amplifier Power and Delay Characterization for Operation under Low-Vdd and Low-voltage Clock Swing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Comparison of On-die Global Clock Distribution Methods for Parallel Serial Links.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009


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