Tara Gheshlaghi

Orcid: 0009-0002-6893-6318

According to our database1, Tara Gheshlaghi authored at least 11 papers between 2024 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Compact Functional Test Pattern Generation for DNNs Using Evolution Strategies.
Proceedings of the 44th IEEE VLSI Test Symposium, 2026

SHOUT - Silent Data Corruption Hunting and Observation Using Transformers.
Proceedings of the 44th IEEE VLSI Test Symposium, 2026

Diagnostic Test Generation for Fault Localization in Printed Neuromorphic Circuits.
Proceedings of the Design, Automation & Test in Europe Conference, 2026

Thermo-NAS: Thermal-resilient ultralow-cost IGZO-based Flexible Neuromorphic Circuits.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025
PRINT-SAFE: Printed Ultra-Low-Cost Electronic X-Design with Scalable Adaptive Fault Endurance.
ACM Trans. Embed. Comput. Syst., 2025

SpikeSynth: Energy-Efficient Adaptive Analog Printed Spiking Neural Networks.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

Automatic Test Pattern Generation for Printed Neuromorphic Circuits.
Proceedings of the IEEE European Test Symposium, 2025

ADAPT-pNC: Mitigating Device Variability and Sensor Noise in Printed Neuromorphic Circuits with SO Adaptive Learnable Filters.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

Power-Constrained Printed Neuromorphic Hardware Training.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024
Neural Architecture Search for Highly Bespoke Robust Printed Neuromorphic Circuits.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

Degradation Monitoring Through Software-controlled On-chip Sensors for RISC-V.
Proceedings of the IEEE European Test Symposium, 2024


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