Sergej Meschkov

Orcid: 0000-0003-1552-589X

According to our database1, Sergej Meschkov authored at least 7 papers between 2021 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2023
New Approaches of Side-Channel Attacks Based on Chip Testing Methods.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

JitSCA: Jitter-based Side-Channel Analysis in Picoscale Resolution.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

Enabling In-Field Parametric Testing for RISC-V Cores.
Proceedings of the IEEE International Test Conference, 2023

SLM ISA and Hardware Extensions for RISC-V Processors.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

Automated Masking of FPGA-Mapped Designs.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Power Side-Channel Attacks and Countermeasures on Computation-in-Memory Architectures and Technologies.
Proceedings of the IEEE European Test Symposium, 2023

2021
Is your secure test infrastructure secure enough? : Attacks based on delay test patterns using transient behavior analysis.
Proceedings of the IEEE International Test Conference, 2021


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