Jonas Krautter

Orcid: 0000-0002-7492-5319

According to our database1, Jonas Krautter authored at least 26 papers between 2018 and 2024.

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Bibliography

2024
Fuzz Wars: The Voltage Awakens - Voltage-Guided Blackbox Fuzzing on FPGAs.
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

MaliGNNoma: GNN-Based Malicious Circuit Classifier for Secure Cloud FPGAs.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024


Degradation Monitoring Through Software-controlled On-chip Sensors for RISC-V.
Proceedings of the IEEE European Test Symposium, 2024

OTFGEncoder - HDC: Hardware-efficient Encoding Techniques for Hyperdimensional Computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

In-Field Detection of Small Delay Defects and Runtime Degradation Using On-Chip Sensors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
New Approaches of Side-Channel Attacks Based on Chip Testing Methods.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

Enabling In-Field Parametric Testing for RISC-V Cores.
Proceedings of the IEEE International Test Conference, 2023

SLM ISA and Hardware Extensions for RISC-V Processors.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

Stress-Resiliency of AI Implementations on FPGAs.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Power2Picture: Using Generative CNNs for Input Recovery of Neural Network Accelerators through Power Side-Channels on FPGAs.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

Power Side-Channel Attacks and Countermeasures on Computation-in-Memory Architectures and Technologies.
Proceedings of the IEEE European Test Symposium, 2023

FPGANeedle: Precise Remote Fault Attacks from FPGA to CPU.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Analysis and Mitigation of Remote Side-Channel and Fault Attacks on the Electrical Level.
PhD thesis, 2022

Remote Fault Attacks in Multitenant Cloud FPGAs.
IEEE Des. Test, 2022

Data Leakage through Self-Terminated Write Schemes in Memristive Caches.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
Is your secure test infrastructure secure enough? : Attacks based on delay test patterns using transient behavior analysis.
Proceedings of the IEEE International Test Conference, 2021

Neural Networks as a Side-Channel Countermeasure: Challenges and Opportunities.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Remote and Stealthy Fault Attacks on Virtualized FPGAs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
CPAmap: On the Complexity of Secure FPGA Virtualization, Multi-Tenancy, and Physical Design.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

Remote Electrical-level Security Threats to Multi-Tenant FPGAs.
IEEE Des. Test, 2020

2019
Mitigating Electrical-level Attacks towards Secure Multi-Tenant FPGAs in the Cloud.
ACM Trans. Reconfigurable Technol. Syst., 2019

Leaky Noise: New Side-Channel Attack Vectors in Mixed-Signal IoT Devices.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

Active Fences against Voltage-based Side Channels in Multi-Tenant FPGAs.
IACR Cryptol. ePrint Arch., 2019

2018
FPGAhammer: Remote Voltage Fault Attacks on Shared FPGAs, suitable for DFA on AES.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

Checking for Electrical Level Security Threats in Bitstreams for Multi-tenant FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2018


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