Tatsuya Kamimura

According to our database, Tatsuya Kamimura authored at least 4 papers between 2011 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2014

A Sub-1mW Class-C-VCO-Based Low Voltage PLL with Ultra-Low-Power Digitally-Calibrated ILFD in 65nm CMOS.

Sho Ikeda, Sang-yeop Lee, Tatsuya Kamimura, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

IEICE Trans. Electron., 2014

A 950μW 5.5-GHz low voltage PLL with digitally-calibrated ILFD and linearized varactor.

Sho Ikeda, Tatsuya Kamimura, Sang-yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2012

A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65 nm CMOS.

Sang-yeop Lee, Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

IEICE Trans. Electron., 2012

2011

A ring-VCO-based injection-locked frequency multiplier using a new pulse generation technique in 65 nm CMOS.

Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Sang-yeop Lee, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

Proceedings of the International SoC Design Conference, 2011