Satoru Tanoi

According to our database, Satoru Tanoi authored at least 10 papers between 1994 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

A 76-Gbit/s 265-GHz CMOS Receiver.

Shinsuke Hara, Ruibing Dong, Sangyeop Lee, Kyoya Takano, Naoya Toshida, Satoru Tanoi, Tatsuo Hagino, Mohamed H. Mubarak, Norihiko Sekine, Issei Watanabe, Akifumi Kasamatsu, Kunio Sakakibara, Shunichi Kubo, Satoshi Miura, Yohtaro Umeda, Takeshi Yoshida, Shuhei Amakawa, Minoru Fujishima

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2014

A High Output Resistance 1.2-V VDD Current Mirror with Deep Submicron Vertical MOSFETs.

Satoru Tanoi, Tetsuo Endoh

IEICE Trans. Electron., 2014

2012

A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65 nm CMOS.

Sang-yeop Lee, Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

IEICE Trans. Electron., 2012

Injection-locked fractional frequency multiplier with automatic reference pulse-selection technique.

Sang-yeop Lee, Hiroyuki Ito, Satoru Tanoi, Noboru Ishihara, Kazuya Masu

IEICE Electron. Express, 2012

2011

A ring-VCO-based injection-locked frequency multiplier using a new pulse generation technique in 65 nm CMOS.

Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Sang-yeop Lee, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

Proceedings of the International SoC Design Conference, 2011

2005

RF-CMOS Implementation of UWB Transceivers and Its Application to Video Transmission.

Akifumi Kasamatsu, Akio Tanaka, Hiroshi Kodama, Satoru Tanoi, Yasuhiro Kaizaki, Juichi Nakada, Masami Hagio, Yoshiaki Kuraishi, Keren Li, Hitoshi Utagawa, Toshiaki Matsui, Ryuji Kohno

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

1998

BIST: required for embedded DRAM.

Satoru Tanoi

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997

On-wafer BIST of a 200-Gb/s failed-bit search for 1-Gb DRAM.

Satoru Tanoi, Yasuhiro Tokunaga, Tetsuya Tanabe, Kazuhiko Takahashi, Atsuhiko Okada, Masahiro Itoh, Yoshiki Nagatomo, Yoshio Ohtsuki, Masaru Uesugi

IEEE J. Solid State Circuits, 1997

1996

A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture.

Satoru Tanoi, Tetsuya Tanabe, Kazuhiko Takahashi, Sanpei Miyamoto, Masaru Uesugi

IEEE J. Solid State Circuits, 1996

1994

A 32-bank 256-Mb DRAM with cache and TAG.

Satoru Tanoi, Yasuhiro Tanaka, Tetsuya Tanabe, Akio Eta, Toshio Inada, Ryoji Hamazaki, Yoshio Ohtsuki, Masaru Uesugi

IEEE J. Solid State Circuits, November, 1994