Kazuya Masu

According to our database1, Kazuya Masu authored at least 100 papers between 1994 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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On csauthors.net:

Bibliography

2020
Distributed Sensing Via Inductively Coupled Single-Transistor Chaotic Oscillators: A New Approach and Its Experimental Proof-of-Concept.
IEEE Access, 2020

2019
Current-Starved Cross-Coupled CMOS Inverter Rings as Versatile Generators of Chaotic and Neural-Like Dynamics Over Multiple Frequency Decades.
IEEE Access, 2019

High-Sensitivity Inertial Sensor Module to Measure Hidden Micro Muscular Sounds.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

2018
A 0.18-µm CMOS time-domain capacitive-sensor interface for sub-1mG MEMS accelerometers.
IEICE Electron. Express, 2018

2017
A - 244-dB FOM High-Frequency Piezoelectric Resonator-Based Cascaded Fractional-N PLL With Sub-ppb-Order Channel-Adjusting Technique.
IEEE J. Solid State Circuits, 2017

A study on young's modulus of electroplated gold cantilevers for MEMS devices.
Proceedings of the 12th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2017

Estimation of energy self-sufficiency rate by EMS simulation using SPICE.
Proceedings of the International Conference on Information and Communication Technology Convergence, 2017

Design of high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Evaluation and modeling of adhesion layer in shock-protection structure for MEMS accelerometer.
Microelectron. Reliab., 2016

Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing.
J. Electron. Test., 2016

An 8.865-GHz -244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Environmental Data Recovery using Polynomial Regression for Large-scale Wireless Sensor Networks.
Proceedings of the SENSORNETS 2016, 2016

Simulation and evaluation of PV power generation for energy management system using SPICE.
Proceedings of the International Conference on Information and Communication Technology Convergence, 2016

Development of high sensitivity CMOS-MEMS inertia sensor and its application to early-stage diagnosis of Parkinson's disease.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
RF-Powered Transceiver With an Energy- and Spectral-Efficient IF-Based Quadrature Backscattering Transmitter.
IEEE J. Solid State Circuits, 2015

13.8 A 5.8GHz RF-powered transceiver with a 113μW 32-QAM transmitter employing the IF-based quadrature backscattering technique.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 0.5-V 1.56-mW 5.5-GHz RF transceiver IC module with J-shaped folded monopole antenna.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 0.5-V 5.8-GHz low-power asymmetrical QPSK/OOK transceiver for wireless sensor network.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
A Variability-Aware Adaptive Test Flow for Test Quality Improvement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

State-Dependence of On-Chip Power Distribution Network Capacitance.
IEICE Trans. Electron., 2014

A Sub-1mW Class-C-VCO-Based Low Voltage PLL with Ultra-Low-Power Digitally-Calibrated ILFD in 65nm CMOS.
IEICE Trans. Electron., 2014

Hypersphere Sampling for Accelerating High-Dimension and Low-Failure Probability Circuit-Yield Analysis.
IEICE Trans. Electron., 2014

An ultra low power pH-monitoring IC with a duty-cycling wireless FM-transmitter.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

An ultra-low-power RF transceiver with a 1.5-pJ/bit maximally-digital impulse-transmitter and an 89.5-μW super-regenerative RSSI.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

A 0.52-V 5.7-GHz low noise sub-sampling PLL with dynamic threshold MOSFET.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

A 950μW 5.5-GHz low voltage PLL with digitally-calibrated ILFD and linearized varactor.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

A 0.5-V 2.5-GHz high-gain low-power regenerative amplifier based on Colpitts oscillator topology in 65-nm CMOS.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
A 60GHz 3-dB tandem coupler using offset broadside-coupled lines on a silicon substrate.
IEICE Electron. Express, 2013

A process-scalable RF transmitter using 90nm and 65nm Si CMOS.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A mixed-design technique for integrated MEMS using a circuit simulator with HDL.
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

Challenges in integration of diverse functionalities on CMOS.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65 nm CMOS.
IEICE Trans. Electron., 2012

RF signal generator using time domain harmonic suppression technique in 90nm CMOS.
IEICE Electron. Express, 2012

Injection-locked fractional frequency multiplier with automatic reference pulse-selection technique.
IEICE Electron. Express, 2012

Optimal design method for chip-area-efficient CMOS low-dropout regulator.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
A Tunable Wideband Frequency Synthesizer Using LC-VCO and Mixer for Reconfigurable Radio Transceivers.
J. Electr. Comput. Eng., 2011

RF CMOS Integrated Circuit: History, Current Status and Future Prospects.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

A 21 V output charge pump circuit with appropriate well-bias supply technique in 0.18 μm Si CMOS.
Proceedings of the International SoC Design Conference, 2011

A ring-VCO-based injection-locked frequency multiplier using a new pulse generation technique in 65 nm CMOS.
Proceedings of the International SoC Design Conference, 2011

2010
A Universal Equivalent Circuit Model for Ceramic Capacitors.
IEICE Trans. Electron., 2010

A Time-Slicing Ring Oscillator for Capturing Time-Dependent Delay Degradation and Power Supply Voltage Fluctuation.
IEICE Trans. Electron., 2010

Linear Time Calculation of On-Chip Power Distribution Network Capacitance Considering State-Dependence.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

A study for the efficiency of transmission energy for different high-frequency communication circuits.
IEICE Electron. Express, 2010

Wide-band, high linear low noise amplifier design in 0.18um CMOS technology.
IEICE Electron. Express, 2010

Path clustering for adaptive test.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Application of generalized scattering matrix for prediction of power supply noise.
Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

Linear time calculation of state-dependent power distribution network capacitance.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Robust importance sampling for efficient SRAM yield analysis.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Scan based process parameter estimation through path-delay inequalities.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Decomposition of drain-current variation into gain-factor and threshold voltage variations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Characterization of On-Chip Multiport Inductors for Small-Area RF Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Accurate Array-Based Measurement for Subthreshold-Current of MOS Transistors.
IEEE J. Solid State Circuits, 2009

2-Port Modeling Technique for Surface-Mount Passive Components Using Partial Inductance Concept.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

One-Shot Voltage-Measurement Circuit Utilizing Process Variation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Tunable CMOS LNA Using a Variable Inductor for a Reconfigurable RF Circuit.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Physical design challenges to nano-CMOS circuits.
IEICE Electron. Express, 2009

A low-phase-noise injection-locked differential ring-VCO with half-integral subharmonic locking in 0.18 µm CMOS.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

Design of CMOS inverter-based output buffers adapting the cherry-hooper broadbanding technique.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

An Adaptive Test for Parametric Faults Based on Statistical Timing Information.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Physical Modeling of MEMS Variable Inductor.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications.
IEEE J. Solid State Circuits, 2008

Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress.
IEICE Trans. Electron., 2008

Reconfigurable RF CMOS Circuit for Cognitive Radio.
IEICE Trans. Commun., 2008

An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

An 8Gbps 2.5mW on-chip pulsed-current-mode transmission line interconnect with a stacked-switch Tx.
Proceedings of the ESSCIRC 2008, 2008

A 1.7-GHz 1.5-mW digitally-controlled FBAR oscillator with 0.03-ppb resolution.
Proceedings of the ESSCIRC 2008, 2008

Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution.
Proceedings of the 45th Design Automation Conference, 2008

Determination of optimal polynomial regression function to decompose on-die systematic and random variations.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Small-area CMOS RF distributed mixer using multi-port inductors.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Low-Loss Distributed Constant Passive Devices Using Wafer-Level Chip Scale Package Technology.
IEICE Trans. Electron., 2007

Adaptable wire-length distribution with tunable occupation probability.
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

Weakness Identification for Effective Repair of Power Distribution Network.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Improvement of power distribution network using correlation-based regression analysis.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

A Multi-Drop Transmission-Line Interconnect in Si LSI.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

A Wideband CMOS LC-VCO Using Variable Inductor.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Statistical Modeling of a Via Distribution for Yield Estimation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

RF Passive Components Using Metal Line on Si CMOS.
IEICE Trans. Electron., 2006

Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Via Distribution Model for Yield Estimation.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Reconfigurable CMOS low noise amplifier for self compensation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Wide Tuning Range LC-VCO Using Variable Inductor for Reconfigurable RF Circuit.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Evaluation of X Architecture Using Interconnect Length Distribution.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Wire Length Distribution Model for System LSI.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Prediction of delay time for future LSI using on-chip transmission line interconnects.
Proceedings of the Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), 2005

Wire Length Distribution Model Considering Core Utilization for System on Chip.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

A dynamic reconfigurable RF circuit architecture.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Evaluation of on-chip transmission line interconnect using wire length distribution.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Inductance-Tuned LC-VCO for Reconfigurable RF Circuit Design.
IEICE Electron. Express, 2004

High speed and low power on-chip micro network circuit with differential transmission line.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004

ULSI Interconnect Length Distribution Model Considering Core Utilization.
Proceedings of the 2004 Design, 2004

Differential transmission line interconnect for high speed and low power global wiring.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2000
Implementation of low power matched filter LSI for IMT-2000.
Proceedings of the 11th IEEE International Symposium on Personal, 2000

Design and implementation of intracell reverse link using approximately synchronized CDMA.
Proceedings of the 11th IEEE International Symposium on Personal, 2000

1994
One chip demodulator using RF front-end SAW correlator for 2.4 GHz asynchronous spread spectrum modem.
Proceedings of the 5th IEEE International Symposium on Personal, 1994


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