Theodor Hillebrand

According to our database1, Theodor Hillebrand authored at least 17 papers between 2016 and 2018.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2018
Design for reliability of generic sensor interface circuits.
Microelectron. Reliab., 2018

On-line monitoring and error correction in sensor interface circuits using digital calibration techniques.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

LUT-Based Stochastic Modeling for Non-Normal Performance Distributions.
Proceedings of the 15th International Conference on Synthesis, 2018

Yield Approximation of Analog Integrated Circuits Under Time-Dependent Variability.
Proceedings of the 15th International Conference on Synthesis, 2018

Topology-Driven Reliability Assessment of Integrated Circuits.
Proceedings of the 25th International Conference "Mixed Design of Integrated Circuits and System", 2018

A New Approach to Threshold Voltage Measurements of Transistors.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Reliability-Aware Multi-Vth Domain Digital Design Assessment.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

2017
Design and Verification of Analog CMOS Circuits Using the <i>g</i> <sub>m</sub>/<i>I</i> <sub>D</sub>-Method with Age-Dependent Degradation Effects.
J. Low Power Electron., 2017

Variation- and degradation-aware stochastic behavioral modeling of analog circuit components.
Proceedings of the 14th International Conference on Synthesis, 2017

Behavioral modeling of a sensor interface circuit including various non-idealities.
Proceedings of the 14th International Conference on Synthesis, 2017

2016
Design and verification of analog CMOS circuits using the gm/ID-method with age-dependent degradation effects.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Degradation and temperature analysis of voltage-controlled ring oscillators for robust and reliable oscillator designs in a 65nm bulk CMOS process.
Proceedings of the 2016 MIXDES, 2016

Parameter identification for behavioral modeling of analog components including degradation.
Proceedings of the 2016 MIXDES, 2016

Stochastic LUT-based reliability-aware design method for operation point dependent CMOS circuits.
Proceedings of the 2016 MIXDES, 2016

Temperature- and aging-resistant inverter for robust and reliable time to digital circuit designs in a 65nm bulk CMOS process.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Online monitoring of NBTI and HCD in beta-multiplier circuits.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Reliability-aware design method for CMOS circuits.
Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016


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