Thomas Boesch
According to our database1,
Thomas Boesch
authored at least 8 papers
between 2016 and 2025.
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Bibliography
2025
NIMA: Near In-Memory High-Precision Accumulation Unit for Heterogeneous Analog/Digital Deep Learning Acceleration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
Multi-Mode Borderguard Controllers for Efficient On-Chip Communication in Heterogeneous Digital/Analog Neural Processing Units.
Proceedings of the Design, Automation & Test in Europe Conference, 2025
2023
A 40-310TOPS/W SRAM-Based All-Digital Up to 4b In-Memory Computing Multi-Tiled NN Accelerator in FD-SOI 18nm for Deep-Learning Edge Applications.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2020
Runtime Design Space Exploration and Mapping of DCNNs for the Ultra-Low-Power Orlando SoC.
ACM Trans. Archit. Code Optim., 2020
2018
Design Space Exploration for Orlando Ultra Low-Power Convolutional Neural Network SoC.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018
2017
14.1 A 2.9TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
Integr., 2016
Proceedings of the Advanced Concepts for Intelligent Vision Systems, 2016