Francesco Conti
Orcid: 0000-0002-7924-933XAffiliations:
- ETH Zurich, Switzerland
- University of Bologna, Italy (PhD 2016)
According to our database1,
Francesco Conti
authored at least 112 papers
between 2013 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
IEEE Robotics Autom. Lett., February, 2024
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing.
IEEE J. Solid State Circuits, January, 2024
CoRR, 2024
An Extreme-Edge TCN-Based Low-Latency Collision-Avoidance Safety System for Industrial Machinery.
IEEE Access, 2024
2023
RedMule: A mixed-precision matrix-matrix operation engine for flexible and energy-efficient on-chip linear algebra and TinyML training acceleration.
Future Gener. Comput. Syst., December, 2023
Reduced precision floating-point optimization for Deep Neural Network On-Device Learning on microcontrollers.
Future Gener. Comput. Syst., December, 2023
Graphene-Based Wireless Agile Interconnects for Massive Heterogeneous Multi-Chip Processors.
IEEE Wirel. Commun., August, 2023
Lightweight Neural Architecture Search for Temporal Convolutional Networks at the Edge.
IEEE Trans. Computers, March, 2023
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine.
CoRR, 2023
A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures.
CoRR, 2023
CoRR, 2023
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing.
CoRR, 2023
Echoes: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays.
CoRR, 2023
DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training.
CoRR, 2023
Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space.
CoRR, 2023
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023
A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
ECHOES: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I<sup>2</sup>S DSP for Flexible Data Acquisition from Microphone Arrays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE European Test Symposium, 2023
Siracusa: A Low-Power On-Sensor RISC-V SoC for Extended Reality Visual Processing in 16nm CMOS.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Specialization meets Flexibility: a Heterogeneous Architecture for High-Efficiency, High-flexibility AR/VR Processing.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the International Conference on Compilers, 2023
Free Bits: Latency Optimization of Mixed-Precision Quantized Neural Networks on the Edge.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
Vau Da Muntanialas: Energy-Efficient Multi-Die Scalable Acceleration of RNN Inference.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
IEEE J. Solid State Circuits, 2022
Fully Onboard AI-Powered Human-Drone Pose Estimation on Ultralow-Power Autonomous Flying Nano-UAVs.
IEEE Internet Things J., 2022
A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Motor-Unit Ordering of Blindly-Separated Surface-EMG Signals for Gesture Recognition.
Proceedings of the Advances in System-Integrated Intelligence, 2022
PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022
ViT-LR: Pushing the Envelope for Transformer-Based on-Device Embedded Continual Learning.
Proceedings of the 13th IEEE International Green and Sustainable Computing Conference, 2022
Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
sEMG Neural Spikes Reconstruction for Gesture Recognition on a Low-Power Multicore Processor.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022
Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes.
IEEE Trans. Emerg. Top. Comput., 2021
IEEE Trans. Computers, 2021
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
Improving Autonomous Nano-Drones Performance via Automated End-to-End Optimization and Deployment of DNNs.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
CoRR, 2021
Fully Onboard AI-powered Human-Drone Pose Estimation on Ultra-low Power Autonomous Flying Nano-UAVs.
CoRR, 2021
A Multi-Precision Bit-Serial Hardware Accelerator IP for Deep Learning Enabled Internet-of-Things.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021
GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode.
Proceedings of the 47th ESSCIRC 2021, 2021
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Pruning In Time (PIT): A Lightweight Network Architecture Optimizer for Temporal Convolutional Networks.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
A Microcontroller is All You Need: Enabling Transformer Execution on Low-Power IoT Endnodes.
Proceedings of the 2021 IEEE International Conference on Omni-Layer Intelligent Systems, 2021
Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH).
Proceedings of the CF '21: Computing Frontiers Conference, 2021
To Buffer, or Not to Buffer? A Case Study on FFT Accelerators for Ultra-Low-Power Multicore Clusters.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
Always-On 674μ W@4GOP/s Error Resilient Binary Neural Networks With Aggressive SRAM Voltage Scaling on a 22-nm IoT End-Node.
IEEE Trans. Circuits Syst., 2020
Robust Real-Time Embedded EMG Recognition Framework Using Temporal Convolutional Networks on a Multicore IoT Processor.
IEEE Trans. Biomed. Circuits Syst., 2020
Introduction to the Special Issue on the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2020).
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge.
IEEE Embed. Syst. Lett., 2020
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Network on RISC-V based IoT End Nodes.
CoRR, 2020
Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors.
CoRR, 2020
Always-On 674uW @ 4GOP/s Error Resilient Binary Neural Networks with Aggressive SRAM Voltage Scaling on a 22nm IoT End-Node.
CoRR, 2020
Memory-Latency-Accuracy Trade-Offs for Continual Learning on a RISC-V Extreme-Edge Node.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020
Temporal Variability Analysis in sEMG Hand Grasp Recognition using Temporal Convolutional Networks.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
IEEE Internet Things J., 2019
PULP-NN: Accelerating Quantized Neural Networks on Parallel Ultra-Low-Power RISC-V Processors.
CoRR, 2019
PULP-NN: A Computing Library for Quantized Neural Network inference at the edge on RISC-V Based Parallel Ultra Low Power Clusters.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
An Open Source and Open Hardware Deep Learning-Powered Visual Navigation Engine for Autonomous Nano-UAVs.
Proceedings of the 15th International Conference on Distributed Computing in Sensor Systems, 2019
DORY: Lightweight memory hierarchy management for deep NN inference on IoT endnodes: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019
2018
NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs.
ACM Trans. Reconfigurable Technol. Syst., 2018
A Heterogeneous Multicore System on Chip for Energy Efficient Brain Inspired Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Architecture-aware design and implementation of CNN algorithms for embedded inference: the ALOHA project.
Proceedings of the 30th International Conference on Microelectronics, 2018
Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018
Quantized NNs as the definitive solution for inference on low-power ARM MCUs?: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018
Chipmunk: A systolically scalable 0.9 mm<sup>2</sup>, 3.08Gop/s/mW @ 1.2 mW accelerator for near-sensor recurrent neural network inference.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018
2017
IEEE Trans. Hum. Mach. Syst., 2017
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors.
IEEE Des. Test, 2017
Chipmunk: A Systolically Scalable 0.9 mm<sup>2</sup>, 3.08 Gop/s/mW @ 1.2 mW Accelerator for Near-Sensor Recurrent Neural Network Inference.
CoRR, 2017
Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS.
Proceedings of the Fourth Workshop on Cryptography and Security in Computing Systems, 2017
An Ultra-Low Power Address-Event Sensor Interface for Energy-Proportional Time-to-Information Extraction.
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores.
J. Signal Process. Syst., 2016
PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision.
J. Signal Process. Syst., 2016
Microprocess. Microsystems, 2016
A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Enabling the heterogeneous accelerator model on ultra-low power microcontroller platforms.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016
2015
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015
A ultra-low-energy convolution engine for fast brain-inspired vision in multicore clusters.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014
Online process transformation for polyhedral process networks in shared-memory MPSoCs.
Proceedings of the 3rd Mediterranean Conference on Embedded Computing, 2014
A Stream Buffer Mechanism for Pervasive Splitting Transformations on Polyhedral Process Networks.
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014
Tightly-coupled hardware support to dynamic parallelism acceleration in embedded shared memory clusters.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2014
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014
2013
Synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013