Cristina Silvano
Orcid: 0000-0003-1668-0883Affiliations:
- Polytechnic University of Milan, Italy
According to our database1,
Cristina Silvano
authored at least 168 papers
between 1995 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2017, "For contributions to energy-efficient computer architectures".
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on orcid.org
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on id.loc.gov
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on dl.acm.org
On csauthors.net:
Bibliography
2023
EXSCALATE: An Extreme-Scale Virtual Screening Platform for Drug Discovery Targeting Polypharmacology to Fight SARS-CoV-2.
IEEE Trans. Emerg. Top. Comput., 2023
A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures.
CoRR, 2023
CoRR, 2023
Tunable and Portable Extreme-Scale Drug Discovery Platform at Exascale: the LIGATE Approach.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
2022
IEEE Trans. Software Eng., 2022
Proceedings of the CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17, 2022
2021
Tunable approximations to control time-to-solution in an HPC molecular docking Mini-App.
J. Supercomput., 2021
An Efficient Monte Carlo-Based Probabilistic Time-Dependent Routing Calculation Targeting a Server-Side Car Navigation System.
IEEE Trans. Emerg. Top. Comput., 2021
EXSCALATE: An extreme-scale in-silico virtual screening platform to evaluate 1 trillion compounds in 60 hours on 81 PFLOPS supercomputers.
CoRR, 2021
2020
Runtime Design Space Exploration and Mapping of DCNNs for the Ultra-Low-Power Orlando SoC.
ACM Trans. Archit. Code Optim., 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
2019
Exploiting OpenMP and OpenACC to accelerate a geometric approach to molecular docking in heterogeneous HPC nodes.
J. Supercomput., 2019
IEEE Trans. Computers, 2019
Microprocess. Microsystems, 2019
Workload- and process-variation aware voltage/frequency tuning for energy efficient performance sustainability of NTC manycores.
Integr., 2019
Exploiting OpenMP & OpenACC to Accelerate a Molecular Docking Mini-App in Heterogeneous HPC Nodes.
CoRR, 2019
Supporting the Scale-Up of High Performance Application to Pre-Exascale Systems: The ANTAREX Approach.
Proceedings of the 27th Euromicro International Conference on Parallel, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
An hybrid approach to accelerate a molecular docking application for virtual screening in heterogeneous nodes: POSTER.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019
2018
Proceedings of the 4th IEEE International Forum on Research and Technology for Society and Industry, 2018
Design Space Pruning and Computational Workload Splitting for Autotuning OpenCL Applications.
Proceedings of the RAPIDO 2018 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2018
Proceedings of the 6th International Workshop on Parallelism in Bioinformatics, 2018
ANTAREX: A DSL-Based Approach to Adaptively Optimizing and Enforcing Extra-Functional Properties in High Performance Computing.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
SOCRATES - A seamless online compiler and system runtime autotuning framework for energy-aware applications.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018
Design Space Exploration for Orlando Ultra Low-Power Convolutional Neural Network SoC.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018
SpringerBriefs in Applied Sciences and Technology, Springer, ISBN: 978-3-319-71489-9, 2018
2017
ACM Trans. Reconfigurable Technol. Syst., 2017
ACM Trans. Reconfigurable Technol. Syst., 2017
MiCOMP: Mitigating the Compiler Phase-Ordering Problem Using Optimization Sub-Sequences and Machine Learning.
ACM Trans. Archit. Code Optim., 2017
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
2016
Guest Editorial: Special Issue on Virtual Prototyping of Parallel and Embedded Systems (ViPES).
ACM Trans. Embed. Comput. Syst., 2016
ACM Trans. Archit. Code Optim., 2016
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016
A System-Level Exploration of Power Delivery Architectures for Near-Threshold Manycores Considering Performance Constraints.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the 7th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 5th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, 2016
Autotuning and adaptivity approach for energy efficient Exascale HPC systems: The ANTAREX approach.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 1st International Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing co-located with 19th International Conference on Design, 2016
Proceedings of the 1st International Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing co-located with 19th International Conference on Design, 2016
Proceedings of the 1st International Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing co-located with 19th International Conference on Design, 2016
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016
Variability-Aware Voltage Island Management for Near-Threshold Computing with Performance Guarantees.
Proceedings of the Near Threshold Computing, Technology, Methods and Applications., 2016
2015
SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
DeSpErate++: An Enhanced Design Space Exploration Framework Using Predictive Simulation Scheduling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Customization of OpenCL applications for efficient task mapping under heterogeneous platform constraints.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
ANTAREX - AutoTuning and Adaptivity appRoach for Energy Efficient eXascale HPC Systems.
Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Combining application adaptivity and system-wide Resource Management on multi-core platforms.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014
OpenCL Application Auto-tuning and Run-Time Resource Management for Multi-core Platforms.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014
Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014
Voltage island management in near threshold manycore architectures to mitigate dark silicon.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
DeSpErate: Speeding-up design space exploration by using predictive simulation scheduling.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Variation-aware voltage island formation for power efficient near-threshold manycore architectures.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
Evaluating orthogonality between application auto-tuning and run-time resource management for adaptive OpenCL applications.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014
Data Parallel Application Adaptivity and System-Wide Resource Management in Many-Core Architectures.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014
2013
ACM Trans. Embed. Comput. Syst., 2013
ARTE: An Application-specific Run-Time managEment framework for multi-cores based on queuing models.
Parallel Comput., 2013
Microprocess. Microsystems, 2013
A framework for Compiler Level statistical analysis over customized VLIW architecture.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Run-time optimization of a dynamically reconfigurable embedded system through performance prediction.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
A meta-model assisted coprocessor synthesis framework for compiler/architecture parameters customization.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Improving simulation speed and accuracy for many-core embedded platforms with ensemble models.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
A Variability-Aware Robust Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints.
ACM Trans. Embed. Comput. Syst., 2012
ACM Trans. Embed. Comput. Syst., 2012
OSCAR: An Optimization Methodology Exploiting Spatial Correlation in Multicore Design Spaces.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Parallel paradigms and run-time management techniques for many-core architectures: the 2PARMA approach.
Proceedings of the 2012 Interconnection Network Architecture, 2012
Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
An exploration methodology for a customizable OpenCL stereo-matching application targeted to an industrial multi-cluster architecture.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
Evaluating Run-time Resource Management Policies for Multi-core Embedded Platforms with the EMME Evaluation Framework.
Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012
2011
Linking run-time resource management of embedded multi-core platforms with automated design-time exploration.
IET Comput. Digit. Tech., 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011
Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip.
Proceedings of the 4th International Workshop on Network on Chip Architectures, 2011
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011
Design Space Exploration for Run-Time Management of a Reconfigurable System for Video Streaming.
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011
2010
Proceedings of the Third International Workshop on Network on Chip Architectures, 2010
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
An industrial design space exploration framework for supporting run-time resource management on multi-core systems.
Proceedings of the Design, Automation and Test in Europe, 2010
Energy-performance design space exploration in SMT architectures exploiting selective load value predictions.
Proceedings of the Design, Automation and Test in Europe, 2010
A correlation-based design space exploration methodology for multi-processor systems-on-chip.
Proceedings of the 47th Design Automation Conference, 2010
Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors.
Proceedings of the ARCS '10, 2010
2009
ReSPIR: A Response Surface-Based Pareto Iterative Refinement for Application-Specific Design Space Exploration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
A design space exploration methodology supporting run-time resource management for multi-processor Systems-on-chip.
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009
Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques.
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009
Proceedings of the Second International Workshop on Network on Chip Architectures, 2009
Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Variability-aware robust design space exploration of chip multiprocessor architectures.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008
An efficient design space exploration methodology for multiprocessor SoC architectures based on response surface methods.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008
Dynamic configuration of application-specific implicit instructions for embedded pipelined processors.
Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008
Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008
Efficiency and scalability of barrier synchronization on NoC based many-core architectures.
Proceedings of the 2008 International Conference on Compilers, 2008
2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Exploration of distributed shared memory architectures for NoC-based multiprocessors.
J. Syst. Archit., 2007
Des. Autom. Embed. Syst., 2007
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007
Mapping and Topology Customization Approaches for Application-Specific STNoC Designs.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
SIGARCH Comput. Archit. News, 2006
An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures.
Proceedings of the IFIP VLSI-SoC 2006, 2006
A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip Architectures.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006
Power/performance hardware optimization for synchronization intensive applications in MPSoCs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
2005
J. Embed. Comput., 2005
Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach.
Integr., 2005
Des. Autom. Embed. Syst., 2005
2004
Multi-objective co-exploration of source code transformations and design space architectures for low-power embedded systems.
Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004
PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures.
Proceedings of the Integrated Circuit and System Design, 2004
Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Plug-in of power models in the StepNP exploration platform: analysis of power/performance trade-offs.
Proceedings of the 2004 International Conference on Compilers, 2004
2003
A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems.
Proceedings of the 2003 ACM Symposium on Applied Computing (SAC), 2003
A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems.
Proceedings of the Integrated Circuit and System Design, 2003
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture.
Proceedings of the 2003 Design, 2003
2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
Des. Autom. Embed. Syst., 2002
A Framework for Modeling and Estimating the Energy Dissipation of VLIW-Based Embedded Systems.
Des. Autom. Embed. Syst., 2002
An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores.
Proceedings of the 2002 Design, 2002
Energy estimation and optimization of embedded VLIW processors based on instruction clustering.
Proceedings of the 39th Design Automation Conference, 2002
2001
Fast system-level exploration of memory architectures driven by energy-delay metrics.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001
2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000
1999
Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study.
Proceedings of the IEEE International Conference On Computer Design, 1999
Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems.
Proceedings of the 1999 Design, 1999
Power estimation for architectural exploration of HW/SW communication on system-level buses.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999
1998
IEEE Trans. Very Large Scale Integr. Syst., 1998
IEEE Trans. Very Large Scale Integr. Syst., 1998
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998
Proceedings of the 1998 Design, 1998
1997
J. Syst. Archit., 1997
Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997
1995
Construction techniques for systematic SEC-DED codes with single byte error detection and partial correction capability for computer memory systems.
IEEE Trans. Inf. Theory, 1995
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995
GECO: A Tool for Automatic Generation of Error Control Codes for Computer Applications.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995