Thomas Chen

Orcid: 0000-0003-3168-9122

Affiliations:
  • University of Michigan, Department of Electrical Engineering and Computer Science, Ann Arbor, MI, USA


According to our database1, Thomas Chen authored at least 10 papers between 2014 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2020
A 1.87-mm<sup>2</sup> 56.9-GOPS Accelerator for Solving Partial Differential Equations.
IEEE J. Solid State Circuits, 2020

2019
A 135-mW 1.70TOPS Sparse Video Sequence Inference SoC for Action Classification.
IEEE J. Solid State Circuits, 2019

An Sram-Based Accelerator for Solving Partial Differential Equations.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A Maximum-Likelihood Sequence Detection Powered ADC-Based Serial Link.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

LEIA: A 2.05mm<sup>2</sup> 140mW lattice encryption instruction accelerator in 40nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
A 1.5-GHz 6.144T Correlations/s 64 × 64 Cross-Correlator With 128 Integrated ADCs for Real-Time Synthetic Aperture Imaging.
IEEE J. Solid State Circuits, 2017

2015
A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding.
IEEE J. Solid State Circuits, 2015

A 640M pixel/s 3.65mW sparse event-driven neuromorphic object recognition processor with on-chip learning.
Proceedings of the Symposium on VLSI Circuits, 2015

2014
Efficient Hardware Architecture for Sparse Coding.
IEEE Trans. Signal Process., 2014

A 6.67mW sparse coding ASIC enabling on-chip learning and inference.
Proceedings of the Symposium on VLSI Circuits, 2014


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