Wei Tang
Orcid: 0000-0001-5204-9728Affiliations:
- University of Michigan, Department of Electrical Engineering and Computer Science, Ann Arbor, MI, USA (PhD 2019)
According to our database1,
Wei Tang
authored at least 14 papers
between 2015 and 2024.
Collaborative distances:
Collaborative distances:
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on orcid.org
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Bibliography
2024
Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration.
IEEE J. Solid State Circuits, April, 2024
2023
Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm<sup>2</sup> AIB 2.0 Interface to Provide Versatile Workload Acceleration.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
VOTA: A Heterogeneous Multicore Visual Object Tracking Accelerator Using Correlation Filters.
IEEE J. Solid State Circuits, 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
A 0.58-mm<sup>2</sup> 2.76-Gb/s 79.8-pJ/b 256-QAM Message-Passing Detector for a 128 × 32 Massive MIMO Uplink System.
IEEE J. Solid State Circuits, 2021
VOTA: A 2.45TFLOPS/W Heterogeneous Multi-Core Visual Object Tracking Accelerator Based on Correlation Filters.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
2019
A 2.4-mm<sup>2</sup> 130-mW MMSE-Nonbinary LDPC Iterative Detector Decoder for 4×4 256-QAM MIMO in 65-nm CMOS.
IEEE J. Solid State Circuits, 2019
CASCADE: Connecting RRAMs to Extend Analog Dataflow In An End-To-End In-Memory Processing Paradigm.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
2018
A 1.8Gb/s 70.6pJ/b 128×16 link-adaptive near-optimal massive MIMO detector in 28nm UTBB-FDSOI.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
LEIA: A 2.05mm<sup>2</sup> 140mW lattice encryption instruction accelerator in 40nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
2016
A 0.58mm<sup>2</sup> 2.76Gb/s 79.8pJ/b 256-QAM massive MIMO message-passing detector.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
2015
18.7 A 2.4mm<sup>2</sup> 130mW MMSE-nonbinary-LDPC iterative detector-decoder for 4×4 256-QAM MIMO in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015