Zhengya Zhang
Orcid: 0000-0001-5963-9018
According to our database1,
Zhengya Zhang
authored at least 105 papers
between 2006 and 2024.
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Bibliography
2024
TetriX: Flexible Architecture and Optimal Mapping for Tensorized Neural Network Processing.
IEEE Trans. Computers, May, 2024
Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration.
IEEE J. Solid State Circuits, April, 2024
TT-CIM: Tensor Train Decomposition for Neural Network in RRAM-Based Compute-in-Memory Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
ANSA: Adaptive Near-Sensor Architecture for Dynamic DNN Processing in Compact Form Factors.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2023
Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm<sup>2</sup> AIB 2.0 Interface to Provide Versatile Workload Acceleration.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
VOTA: A Heterogeneous Multicore Visual Object Tracking Accelerator Using Correlation Filters.
IEEE J. Solid State Circuits, 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference.
IEEE J. Solid State Circuits, 2021
A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture.
IEEE J. Solid State Circuits, 2021
A 0.58-mm<sup>2</sup> 2.76-Gb/s 79.8-pJ/b 256-QAM Message-Passing Detector for a 128 × 32 Massive MIMO Uplink System.
IEEE J. Solid State Circuits, 2021
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
VOTA: A 2.45TFLOPS/W Heterogeneous Multi-Core Visual Object Tracking Accelerator Based on Correlation Filters.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Exploration of Energy-Efficient Architecture for Graph-Based Point-Cloud Deep Learning.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021
Point-X: A Spatial-Locality-Aware Architecture for Energy-Efficient Graph-Based Point-Cloud Deep Learning.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
Proceedings of the IEEE Global Communications Conference, 2021
A 256Gb/s/mm-shoreline AIB-Compatible 16nm FinFET CMOS Chiplet for 2.5D Integration with Stratix 10 FPGA on EMIB and Tiling on Silicon Interposer.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
A 1.87-mm<sup>2</sup> 56.9-GOPS Accelerator for Solving Partial Differential Equations.
IEEE J. Solid State Circuits, 2020
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2020
QuickNN: Memory and Performance Optimization of k-d Tree Based Nearest Neighbor Search for 3D Point Clouds.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 2.4-mm<sup>2</sup> 130-mW MMSE-Nonbinary LDPC Iterative Detector Decoder for 4×4 256-QAM MIMO in 65-nm CMOS.
IEEE J. Solid State Circuits, 2019
IEEE J. Solid State Circuits, 2019
SNAP: A 1.67 - 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 3.25Gb/s, 13.2pJ/b, 0.64mm<sup>2</sup> Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
CASCADE: Connecting RRAMs to Extend Analog Dataflow In An End-To-End In-Memory Processing Paradigm.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
A 2048-Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
IEEE Trans. Multi Scale Comput. Syst., 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 2.56-mm<sup>2</sup> 718GOPS Configurable Spiking Convolutional Sparse Coding Accelerator in 40-nm CMOS.
IEEE J. Solid State Circuits, 2018
A 1920 × 1080 30-frames/s 2.3 TOPS/W Stereo-Depth Processor for Energy-Efficient Autonomous Navigation of Micro Aerial Vehicles.
IEEE J. Solid State Circuits, 2018
Proceedings of the International Joint Conference SOCO'18-CISIS'18-ICEUTE'18, 2018
A 1.8Gb/s 70.6pJ/b 128×16 link-adaptive near-optimal massive MIMO detector in 28nm UTBB-FDSOI.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 0.23mW Heterogeneous Deep-Learning Processor Supporting Dynamic Execution of Conditional Neural Networks.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
LEIA: A 2.05mm<sup>2</sup> 140mW lattice encryption instruction accelerator in 40nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
Inference and Learning Hardware Architecture for Neuro- Inspired Sparse Coding Algoerithm.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
2017
A 1.5-GHz 6.144T Correlations/s 64 × 64 Cross-Correlator With 128 Integrated ADCs for Real-Time Synthetic Aperture Imaging.
IEEE J. Solid State Circuits, 2017
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017
20.7 A 13.8µW binaural dual-microphone digital ANSI S1.11 filter bank for hearing aids with zero-short-circuit-current logic in 65nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
3.7 A 1920×1080 30fps 2.3TOPS/W stereo-depth processor for robust autonomous navigation.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Post-Processing Methods for Improving Coding Gain in Belief Propagation Decoding of Polar Codes.
Proceedings of the 2017 IEEE Global Communications Conference, 2017
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
A 2.56mm<sup>2</sup> 718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
3.2 Gbps Channel-Adaptive Configurable MIMO Detector for Multi-Mode Wireless Communication.
J. Signal Process. Syst., 2016
Robustness of text-based completely automated public turing test to tell computers and humans apart.
IET Inf. Secur., 2016
A 0.58mm<sup>2</sup> 2.76Gb/s 79.8pJ/b 256-QAM massive MIMO message-passing detector.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the 23rd Annual Network and Distributed System Security Symposium, 2016
Architecture and optimization of high-throughput belief propagation decoding of polar codes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Geoscience and Remote Sensing Symposium, 2016
A 5.5GHz 0.84TOPS/mm<sup>2</sup> neural network engine with stream architecture and resonant clock mesh.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
Error patterns in belief propagation decoding of polar codes and their mitigation methods.
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016
2015
An FPGA-Based Transient Error Simulator for Resilient Circuit and System Design and Evaluation.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
IEEE J. Solid State Circuits, 2015
A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding.
IEEE J. Solid State Circuits, 2015
IEEE J. Solid State Circuits, 2015
Proceedings of the Symposium on VLSI Circuits, 2015
A 640M pixel/s 3.65mW sparse event-driven neuromorphic object recognition processor with on-chip learning.
Proceedings of the Symposium on VLSI Circuits, 2015
18.7 A 2.4mm<sup>2</sup> 130mW MMSE-nonbinary-LDPC iterative detector-decoder for 4×4 256-QAM MIMO in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
A 934MHz 9Gb/s 3.2pJ/b/iteration charge-recovery LDPC decoder with in-package inductors.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE J. Solid State Circuits, 2014
An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS.
IEEE J. Solid State Circuits, 2014
Proceedings of the Symposium on VLSI Circuits, 2014
Proceedings of the Symposium on VLSI Circuits, 2014
3.2Gbps channel-adaptive configurable MIMO detector for multi-mode wireless communication.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
A 1.15Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 470mV 2.7mW feature extraction-accelerator for micro-autonomous vehicle navigation in 28nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the IEEE International Conference on Acoustics, 2013
An FPGA-based transient error simulator for evaluating resilient system designs (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013
2012
IEEE Trans. Signal Process., 2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
The Cycle Consistency Matrix Approach to LDPC Absorbing Sets in Separable Circulant-Based Codes
CoRR, 2012
A 1.6-mm<sup>2</sup> 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM.
Proceedings of the Symposium on VLSI Circuits, 2012
High-throughput architecture and implementation of regular (2, dc) nonbinary LDPC decoders.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Reconfigurable architecture and automated design flow for rapid FPGA-based LDPC code emulation.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012
2011
Proceedings of the 2011 IEEE International Symposium on Information Theory Proceedings, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Hardware acceleration of iterative image reconstruction for X-ray computed tomography.
Proceedings of the IEEE International Conference on Acoustics, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
IEEE Trans. Inf. Theory, 2010
IEEE J. Solid State Circuits, 2010
2009
Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices.
IEEE Trans. Commun., 2009
Predicting error floors of structured LDPC codes: deterministic bounds and estimates.
IEEE J. Sel. Areas Commun., 2009
2008
Proceedings of the 2008 IEEE International Symposium on Information Theory, 2008
Proceedings of the Global Communications Conference, 2008. GLOBECOM 2008, New Orleans, LA, USA, 30 November, 2008
2007
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Proceedings of IEEE International Conference on Communications, 2007
Proceedings of IEEE International Conference on Communications, 2007
2006
Investigation of Error Floors of Structured Low-Density Parity-Check Codes by Hardware Emulation.
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006