Jorge Pernillo

According to our database, Jorge Pernillo authored at least 7 papers between 2011 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

A 400Gb/s Transceiver for PAM-4 Optical Direct-Detect Application in 16nm FinFET.

Chang-Feng Loi, A. Mellati, Amber Tan, A. Farhoodfar, Arun Tiruvur, Belal Helal, Bob Killips, Farshid Rafiee Rad, Jamal Riani, Jorge Pernillo, J. Sun, J. Wong, K. Abdelhalim, K. Gopalakrishnan, Kwang Young Kim, Lawrence Tse, M. Davoodi, Michael Q. Le, M. Zhang, M. Talegaonkar, P. Prabha, Ravindran Mohanavelu, S. Chong, Simon Forey, S. Netto, Sudeep Bhoja, W. Liew, Y. Duan, Y. Liao

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018

A Mismatch-Immune 12-Bit SAR ADC With Completely Reconfigurable Capacitor DAC.

Nicholas Collins, Andres Tamez, Lu Jie, Jorge Pernillo, Michael P. Flynn

IEEE Trans. Circuits Syst. II Express Briefs, 2018

2017

A 1.5-GHz 6.144T Correlations/s 64 × 64 Cross-Correlator With 128 Integrated ADCs for Real-Time Synthetic Aperture Imaging.

John Bell, Phil Knag, Shuanghong Sun, Yong Lim, Thomas Chen, Jeffrey Fredenburg, Chia-Hsiang Chen, Chunyang Zhai, Aaron Z. Rocca, Nicholas Collins, Andres Tamez, Jorge Pernillo, Justin M. Correll, Alan B. Tanner, Zhengya Zhang, Michael P. Flynn

IEEE J. Solid State Circuits, 2017

A background calibrated 28GS/s 8b interleaved SAR ADC in 28nm CMOS.

Michael Q. Le, James Gorecki, Jamal Riani, Jorge Pernillo, A. Tan, K. Gopalakrishnan, Belal Helal, Pulkit Khandelwal, Chang-Feng Loi, Irene Quek, P. Wong, Aaron Buchwald

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016

3.4 A 40/50/100Gb/s PAM-4 Ethernet transceiver in 28nm CMOS.

Karthik Gopalakrishnan, Alan Ren, Amber Tan, Arash Farhood, Arun Tiruvur, Belal Helal, Chang-Feng Loi, Chris Jiang, Halil Cirit, Irene Quek, Jamal Riani, James Gorecki, Jennifer Wu, Jorge Pernillo, Lawrence Tse, Michael Q. Le, Mohammad Ranjbar, Pui-Shan Wong, Pulkit Khandelwal, Rajesh Narayanan, Ravindran Mohanavelu, Sameer Herlekar, Sudeep Bhoja, Vlad Shvydun

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2013

A 9b 2GS/s 45mW 2X-interleaved ADC.

Jorge Pernillo, Michael P. Flynn

Proceedings of the ESSCIRC 2013, 2013

2011

A 1.5-GS/s Flash ADC With 57.7-dB SFDR and 6.4-Bit ENOB in 90 nm Digital CMOS.

Jorge Pernillo, Michael P. Flynn

IEEE Trans. Circuits Syst. II Express Briefs, 2011