Thomas M. Niermann

According to our database, Thomas M. Niermann authored at least 8 papers between 1988 and 1997.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1997

A genetic algorithm framework for test generation.

Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

1994

Sequential Circuit Test Generation in a Genetic Algorithm Framework.

Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann

Proceedings of the 31st Conference on Design Automation, 1994

1992

Test compaction for sequential circuits.

Thomas M. Niermann, Rabindra K. Roy, Janak H. Patel, Jacob A. Abraham

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

PROOFS: a fast, memory-efficient sequential circuit fault simulator.

Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

1991

Techniques for sequential circuit automatic test generation

Thomas M. Niermann

PhD thesis, 1991

Methods for Reducing Events in Sequential Circuit Fault Simulation.

Elizabeth M. Rudnick, Thomas M. Niermann, Janak H. Patel

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

HITEC: a test generation package for sequential circuits.

Thomas M. Niermann, Janak H. Patel

Proceedings of the conference on European design automation, 1991

1988

Compaction of ATPG-generated test sequences for sequential circuits.

Rabindra K. Roy, Thomas M. Niermann, Janak H. Patel, Jacob A. Abraham, Resve A. Saleh

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988