Thomas P. Kelliher

According to our database1, Thomas P. Kelliher authored at least 16 papers between 1991 and 2006.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2006
HELLAS: a specialized architecture for interactive deformable object modeling.
Proceedings of the 44st Annual Southeast Regional Conference, 2006

2005
An Analysis of Iterative Deformable Solid Object Modeling.
Proceedings of The 2005 International Conference on Modeling, 2005

2003
Specialized hardware for deformable object modeling.
IEEE Trans. Circuits Syst. Video Technol., 2003

2000
The design of the MGAP-2: a micro-grained massively parallel array.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Hardware/Software Co-design for Real-Time Physical Modeling.
Proceedings of the 2000 IEEE International Conference on Multimedia and Expo, 2000

SPARTA: Simulation of Physics on a Real-Time Architecture.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

1999
Aggressive Dynamic Execution of Decoded Traces.
J. VLSI Signal Process., 1999

The Design of a Register Renaming Unit.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1997
The MGAP Family of Processor Arrays.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

1996
Simultaneous speech segmentation and phoneme recognition using dynamic programming.
Proceedings of the 1996 IEEE International Conference on Acoustics, 1996

1995
The MGAP-2: an advanced, massively parallel VLSI signal processor.
Proceedings of the 1995 International Conference on Acoustics, 1995

1993
The design and implementation of the Arithmetic Cube II, a VLSI signal processing system.
IEEE Trans. Very Large Scale Integr. Syst., 1993

A systolic VLSI architecture for multi-dimensional transforms.
Proceedings of the IEEE International Conference on Acoustics, 1993

1992
ELM-A Fast Addition Algorithm Discovered by a Program.
IEEE Trans. Computers, 1992

Implementing a family of high performance, micrograined architectures.
Proceedings of the Application Specific Array Processors, 1992

1991
The arithmetic cube II: a second generation VLSI DSP processor.
Proceedings of the 1991 International Conference on Acoustics, 1991


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