Mohan Vishwanath

According to our database1, Mohan Vishwanath authored at least 23 papers between 1991 and 1998.

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Bibliography

1998
A Very Efficient Storage Structure for DWT and IDWT Filters.
J. VLSI Signal Process., 1998

1997
A progressive Ziv-Lempel algorithm for image compression.
Proceedings of the Compression and Complexity of SEQUENCES 1997, 1997

1996
Architectures for wavelet transforms: A survey.
J. VLSI Signal Process., 1996

An optimal time multiplication free algorithm for edge detection on a mesh.
J. VLSI Signal Process., 1996

A low power video encoder with power, memory and bandwidth scalability.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Improving the performance of hierarchical vector quantization using segmentation.
Proceedings of the Proceedings 1996 International Conference on Image Processing, 1996

A Common Architecture For The DWT and IDWT.
Proceedings of the 1996 International Conference on Application-Specific Systems, 1996

1995
Efficient realizations of the discrete and continuous wavelet transforms: from single chip implementations to mappings on SIMD array computers.
IEEE Trans. Signal Process., 1995

A survey of architectures for the discrete and continuous wavelet transforms.
Proceedings of the 1995 International Conference on Acoustics, 1995

Hierarchical Vector Quantization of Perceptually Weighted Block Transforms.
Proceedings of the IEEE Data Compression Conference, 1995

1994
The recursive pyramid algorithm for the discrete wavelet transform.
IEEE Trans. Signal Process., 1994

An Efficient Algorithm for Hierarchical Compression of Video.
Proceedings of the Proceedings 1994 International Conference on Image Processing, 1994

A VLSI architecture for real-time hierarchical encoding/decoding of video using the wavelet transform.
Proceedings of ICASSP '94: IEEE International Conference on Acoustics, 1994

Algorithms and architectures for hierarchical compression of video.
Proceedings of the International Conference on Application Specific Array Processors, 1994

1993
The design and implementation of the Arithmetic Cube II, a VLSI signal processing system.
IEEE Trans. Very Large Scale Integr. Syst., 1993

A new blocked IIR algorithm.
Proceedings of the IEEE International Conference on Acoustics, 1993

Edge detection using fine-grained parallelism in VLSI.
Proceedings of the IEEE International Conference on Acoustics, 1993

1992
ECube: An Efficient Architecture for Analyzing Time-Varying Spectra.
Proceedings of the Fifth International Conference on VLSI Design, 1992

An AT/sup 2/ lower bound for wavelet transforms in VLSI.
Proceedings of the 1992 IEEE International Conference on Acoustics, 1992

Discrete wavelet transforms in VLSI.
Proceedings of the Application Specific Array Processors, 1992

Implementing a family of high performance, micrograined architectures.
Proceedings of the Application Specific Array Processors, 1992

1991
The arithmetic cube II: a second generation VLSI DSP processor.
Proceedings of the 1991 International Conference on Acoustics, 1991

The Arithmetic Cube: error analysis and simulation.
Proceedings of the Application Specific Array Processors, 1991


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