Ting-Shuo Hsu

According to our database1, Ting-Shuo Hsu authored at least 13 papers between 2012 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph.
Proceedings of the IEEE International Test Conference, 2021

2020
An ISA-level Accurate Fault Simulator for System-level Fault Analysis.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019
NNSim: A Fast and Accurate SystemC/TLM Simulator for Deep Convolutional Neural Network Accelerators.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

2017
Design space exploration with a cycle-accurate systemC/TLM DRAM controller model.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

Post-Silicon Test Flow for Aging Prediction.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

2015
A fast and accurate network-on-chip timing simulator with a flit propagation model.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Design of a scalable many-core processor for embedded applications.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Chip clustering with mutual information on multiple clock tests and its application to yield tuning.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013
Design of high-throughput Inter-PE communication with application-level flow control protocol for many-core architectures.
Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, 2013

A Region-Based Framework for Design Feature Identification of Systematic Process Variations.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Test Cost Reduction for Performance Yield Recovery by Classification of Multiple-Clock Test Data.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Design and analysis of a many-core processor architecture for multimedia applications.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2012


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