Chih-Tsun Huang

According to our database1, Chih-Tsun Huang authored at least 61 papers between 1997 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2017
Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

Design space exploration with a cycle-accurate systemC/TLM DRAM controller model.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

2016

2015
Application-level embedded communication tracer for many-core systems.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Design of a scalable many-core processor for embedded applications.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Design of low-cost elliptic curve cryptographic engines for ubiquitous security.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

2013
AC-Plus Scan Methodology for Small Delay Testing and Characterization.
IEEE Trans. VLSI Syst., 2013

Design of high-throughput Inter-PE communication with application-level flow control protocol for many-core architectures.
Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, 2013

2012
Design and analysis of a many-core processor architecture for multimedia applications.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2012

2011
Energy-Adaptive Dual-Field Processor for High-Performance Elliptic Curve Cryptographic Applications.
IEEE Trans. VLSI Syst., 2011

Hardware/software co-designed accelerator for vector graphics applications.
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011

A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing.
Proceedings of the 48th Design Automation Conference, 2011

Reliability analysis and improvement for multi-level non-volatile memories with soft information.
Proceedings of the 48th Design Automation Conference, 2011

TurboVG: A HW/SW co-designed multi-core OpenVG accelerator for vector graphics applications with embedded power profiler.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Single- and Multi-core Configurable AES Architectures for Flexible Security.
IEEE Trans. VLSI Syst., 2010

High-performance architecture for Elliptic Curve Cryptography over binary field.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009
A Highly Efficient Cipher Processor for Dual-Field Elliptic Curve Cryptography.
IEEE Trans. on Circuits and Systems, 2009

2008
Elixir: High-Throughput Cost-Effective Dual-Field Processors and the Design Framework for Elliptic Curve Cryptography.
IEEE Trans. VLSI Syst., 2008

An embedded infrastructure of debug and trace interface for the DSP platform.
Proceedings of the 45th Design Automation Conference, 2008

Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
Optimization of Pattern Matching Circuits for Regular Expression on FPGA.
IEEE Trans. VLSI Syst., 2007

BIST-based diagnosis scheme for field programmable gate array interconnect delay faults.
IET Computers & Digital Techniques, 2007

A prototype of a wireless-based test system.
Proceedings of the 2007 IEEE International SOC Conference, 2007

A High-Throughput Low-Power AES Cipher for Network Applications.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Optimization of regular expression pattern matching circuits on FPGA.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

A network security processor design based on an integrated SOC design and test platform.
Proceedings of the 43rd Design Automation Conference, 2006

2005
A BIST Scheme for FPGA Interconnect Delay Faults.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

A systematic approach to reducing semiconductor memory test time in mass production.
Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

Design and test of a scalable security processor.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A configurable AES processor for enhanced security.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
An SOC Test Integration Platform and Its Industrial Realization.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

An Application-Independent Delay Testing Methodology for Island-Style FPGA.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Failure Factor Based Yield Enhancement for SRAM Designs.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

On Test and Diagnostics of Flash Memories.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

An HMAC processor with integrated SHA-1 and MD5 algorithms.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Built-in redundancy analysis for memory yield improvement.
IEEE Trans. Reliability, 2003

A high-throughput low-cost AES processor.
IEEE Communications Magazine, 2003

Test and Diagnosis of Word-Oriented Multiport Memories.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Fault Pattern Oriented Defect Diagnosis for Memories.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

FAME: A Fault-Pattern Based Memory Failure Analysis Framework.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Design of a scalable RSA and ECC crypto-processor.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

A highly efficient AES cipher chip.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Fault simulation and test algorithm generation for random accessmemories.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Diagonal Test and Diagnostic Schemes for Flash Memorie.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Flash Memory Built-In Self-Test Using March-Like Algorithm.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Test Scheduling of BISTed Memory Cores for SOC.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Test Scheduling and Test Access Architecture Optimization for System-on-Chip.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
March-based RAM diagnosis algorithms for stuck-at and coupling faults.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories.
Proceedings of the 38th Design Automation Conference, 2001

A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
Simulation-Based Test Algorithm Generation for Random Access Memories.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Error Catch and Analysis for Semiconductor Memories Using March Tests.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

BRAINS: A BIST Compiler for Embedded Memories.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

A programmable built-in self-test core for embedded memories.
Proceedings of ASP-DAC 2000, 2000

1999
A Programmable BIST Core for Embedded DRAM.
IEEE Design & Test of Computers, 1999

RAMSES: A Fast Memory Fault Simulator.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

1997
High-speed C-testable systolic array design for Galois-field inversion.
Proceedings of the European Design and Test Conference, 1997


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