Jing-Jia Liou

According to our database1, Jing-Jia Liou authored at least 54 papers between 2000 and 2019.

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Bibliography

2019
NNSim: A Fast and Accurate SystemC/TLM Simulator for Deep Convolutional Neural Network Accelerators.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

A FPGA Implementation of Farneback Optical Flow by High-Level Synthesis.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2017
Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

Design space exploration with a cycle-accurate systemC/TLM DRAM controller model.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

Post-Silicon Test Flow for Aging Prediction.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

2015
Pseudo-Multiple-Exposure-Based Tone Fusion With Local Region Adjustment.
IEEE Trans. Multim., 2015

Cost reduction of system-level tests with stressed structural tests and SVM.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

A fast and accurate network-on-chip timing simulator with a flit propagation model.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Design of a scalable many-core processor for embedded applications.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Chip clustering with mutual information on multiple clock tests and its application to yield tuning.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013
AC-Plus Scan Methodology for Small Delay Testing and Characterization.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Design of high-throughput Inter-PE communication with application-level flow control protocol for many-core architectures.
Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, 2013

A Region-Based Framework for Design Feature Identification of Systematic Process Variations.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Test Cost Reduction for Performance Yield Recovery by Classification of Multiple-Clock Test Data.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

On error modeling of electrical bugs for post-silicon timing validation.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Design and analysis of a many-core processor architecture for multimedia applications.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2012

2011
Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits with Clock Networks.
J. Circuits Syst. Comput., 2011

A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing.
Proceedings of the 48th Design Automation Conference, 2011

Diagnosis-assisted supply voltage configuration to increase performance yield of cell-based designs.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

TurboVG: A HW/SW co-designed multi-core OpenVG accelerator for vector graphics applications with embedded power profiler.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Automatic Test Wrapper Synthesis for a Wireless ATE Platform.
IEEE Des. Test Comput., 2010

AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009
A Non-Intrusive and Accurate Inspection Method for Segment Delay Variabilities.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Multiple-Core under Test Architecture for HOY Wireless Testing Platform.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Diagnosis Framework for Locating Failed Segments of Path Delay Faults.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

High Quality Pattern Generation for Delay Defects with Functional Sensitized Paths.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
BIST-based diagnosis scheme for field programmable gate array interconnect delay faults.
IET Comput. Digit. Tech., 2007

Handling Pattern-Dependent Delay Faults in Diagnosis.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

A prototype of a wireless-based test system.
Proceedings of the 2007 IEEE International SOC Conference, 2007

An efficient SAT-based path delay fault ATPG with an unified sensitization model.
Proceedings of the 2007 IEEE International Test Conference, 2007

Extraction of Statistical Timing Profiles Using Test Data.
Proceedings of the 44th Design Automation Conference, 2007

2006
Exploring linear structures of critical path delay faults to reduce test efforts.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Enhancing Diagnosis Resolution For Delay Faults By Path Extension Method.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005
A BIST Scheme for FPGA Interconnect Delay Faults.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Diagnosis framework for locating failed segments of path delay faults.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004
Critical path selection for delay fault testing based upon a statistical timing model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

An Application-Independent Delay Testing Methodology for Island-Style FPGA.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

2003
Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Diagnosis of Delay Defects Using Statistical Timing Models.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

On Structural vs. Functional Testing for Delay Faults.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step.
Proceedings of the 2003 Design, 2003

Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models.
Proceedings of the 40th Design Automation Conference, 2003

Experience in critical path selection for deep sub-micron delay test and timing validation.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

On theoretical and practical considerations of path selection for delay fault testing.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Enhancing test efficiency for delay fault testing using multiple-clocked schemes.
Proceedings of the 39th Design Automation Conference, 2002

False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation.
Proceedings of the 39th Design Automation Conference, 2002

2001
Delay testing considering crosstalk-induced effects.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Fast Statistical Timing Analysis By Probabilistic Event Propagation.
Proceedings of the 38th Design Automation Conference, 2001

2000
Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Performance sensitivity analysis using statistical method and its applications to delay.
Proceedings of ASP-DAC 2000, 2000


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