Tobias Schneider

Orcid: 0000-0002-6849-5949

Affiliations:
  • NXP Semiconductors, Austria
  • Université catholique de Louvain, Belgium (former)
  • Ruhr University Bochum, Germany (former)


According to our database1, Tobias Schneider authored at least 35 papers between 2013 and 2024.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
Exploiting Small-Norm Polynomial Multiplication with Physical Attacks Application to CRYSTALS-Dilithium.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

2023
From MLWE to RLWE: A Differential Fault Attack on Randomized & Deterministic Dilithium.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

Protecting Dilithium against Leakage Revisited Sensitivity Analysis and Improved Implementations.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

2022
Post-Quantum Authenticated Encryption against Chosen-Ciphertext Side-Channel Attacks.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Systematic Study of Decryption and Re-Encryption Leakage: the Case of Kyber.
IACR Cryptol. ePrint Arch., 2022

Leveling Dilithium against Leakage: Revisited Sensitivity Analysis and Improved Implementations.
IACR Cryptol. ePrint Arch., 2022

2021
Masking Kyber: First- and Higher-Order Implementations.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

Reducing risks through simplicity: high side-channel security for lazy engineers.
J. Cryptogr. Eng., 2021

The Matrix Reloaded: Multiplication Strategies in FrodoKEM.
IACR Cryptol. ePrint Arch., 2021

Cyber Resilience for Self-Monitoring IoT Devices.
Proceedings of the IEEE International Conference on Cyber Security and Resilience, 2021

2020
High-Speed Masking for Polynomial Comparison in Lattice-based KEMs.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

Impeccable Circuits.
IEEE Trans. Computers, 2020

2019
Glitch-Resistant Masking Revisited or Why Proofs in the Robust Probing Model are Needed.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

Multi-Tuple Leakage Detection and the Dependent Signal Issue.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

Efficiently Masking Binomial Sampling at Arbitrary Orders for Lattice-Based Crypto.
IACR Cryptol. ePrint Arch., 2019

2018
Hardware-based countermeasures against physical attacks.
PhD thesis, 2018

Practical CCA2-Secure and Masked Ring-LWE Implementation.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

Leakage Detection with the x2-Test.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

Impeccable Circuits.
IACR Cryptol. ePrint Arch., 2018

2017
Strong 8-bit Sboxes with efficient masking in hardware extended version.
J. Cryptogr. Eng., 2017

Amortizing Randomness Complexity in Private Circuits.
IACR Cryptol. ePrint Arch., 2017

Gimli: a cross-platform permutation.
IACR Cryptol. ePrint Arch., 2017

SPARX - A side-channel protected processor for ARX-based cryptography.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Leakage assessment methodology - Extended version.
J. Cryptogr. Eng., 2016

Bridging the Gap: Advanced Tools for Side-Channel Leakage Estimation beyond Gaussian Templates and Histograms.
IACR Cryptol. ePrint Arch., 2016

ParTI - Towards Combined Hardware Countermeasures against Side-Channel and Fault-Injection Attacks.
IACR Cryptol. ePrint Arch., 2016

Side-Channel Analysis Protection and Low-Latency in Action - case study of PRINCE and Midori.
IACR Cryptol. ePrint Arch., 2016

Improved Side-Channel Analysis Attacks on Xilinx Bitstream Encryption of 5, 6, and 7 Series.
IACR Cryptol. ePrint Arch., 2016

Strong 8-bit Sboxes with Efficient Masking in Hardware.
IACR Cryptol. ePrint Arch., 2016

ParTI: Towards Combined Hardware Countermeasures against Side-Channeland Fault-Injection Attacks.
Proceedings of the ACM Workshop on Theory of Implementation Security, 2016

2015
Robust and One-Pass Parallel Computation of Correlation-Based Attacks at Arbitrary Order.
IACR Cryptol. ePrint Arch., 2015

Arithmetic Addition over Boolean Masking - Towards First- and Second-Order Resistance in Hardware.
IACR Cryptol. ePrint Arch., 2015

Leakage Assessment Methodology - a clear roadmap for side-channel evaluations.
IACR Cryptol. ePrint Arch., 2015

2014
Cryptographic Algorithms on the GA144 Asynchronous Multi-Core Processor - Implementation and Side-Channel Analysis.
J. Signal Process. Syst., 2014

2013
Efficient implementation of cryptographic primitives on the GA144 multi-core architecture.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013


  Loading...