Olivier Bronchain

Orcid: 0000-0001-7595-718X

Affiliations:
  • Catholic University of Louvain, Louvain-la-Neuve, Belgium (PhD 2022)


According to our database1, Olivier Bronchain authored at least 29 papers between 2018 and 2024.

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Timeline

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Bibliography

2024
Exploiting Small-Norm Polynomial Multiplication with Physical Attacks Application to CRYSTALS-Dilithium.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

2023
SCALib: A Side-Channel Analysis Library.
J. Open Source Softw., June, 2023

From MLWE to RLWE: A Differential Fault Attack on Randomized & Deterministic Dilithium.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

Enabling FrodoKEM on Embedded Devices.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

Protecting Dilithium against Leakage Revisited Sensitivity Analysis and Improved Implementations.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

PQ.V.ALU.E: Post-Quantum RISC-V Custom ALU Extensions on Dilithium and Kyber.
IACR Cryptol. ePrint Arch., 2023

2022
Worst-case side-channel security: from evaluation of countermeasures to new designs.
PhD thesis, 2022

Efficient Profiled Side-Channel Analysis of Masked Implementations, Extended.
IEEE Trans. Inf. Forensics Secur., 2022

Bitslicing Arithmetic/Boolean Masking Conversions for Fun and Profit with Application to Lattice-Based KEMs.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Bitslice Masking and Improved Shuffling: How and When to Mix Them in Software?
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Systematic Study of Decryption and Re-Encryption Leakage: the Case of Kyber.
IACR Cryptol. ePrint Arch., 2022

Leveling Dilithium against Leakage: Revisited Sensitivity Analysis and Improved Implementations.
IACR Cryptol. ePrint Arch., 2022

2021
MOE: Multiplication Operated Encryption with Trojan Resilience.
IACR Trans. Symmetric Cryptol., 2021

Breaking Masked Implementations with Many Shares on 32-bit Software Platforms or When the Security Order Does Not Matter.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

Improved Leakage-Resistant Authenticated Encryption based on Hardware AES Coprocessors.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

Side-channel analysis of a learning parity with physical noise processor.
J. Cryptogr. Eng., 2021

Reducing risks through simplicity: high side-channel security for lazy engineers.
J. Cryptogr. Eng., 2021

Give Me 5 Minutes: Attacking ASCAD with a Single Side-Channel Trace.
IACR Cryptol. ePrint Arch., 2021

How to fool a black box machine learning based side-channel security evaluation.
Cryptogr. Commun., 2021

A stealthy Hardware Trojan based on a Statistical Fault Attack.
Cryptogr. Commun., 2021

Security Analysis of Deterministic Re-keying with Masking and Shuffling: Application to ISAP.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2021

2020
Spook: Sponge-Based Leakage-Resistant Authenticated Encryption with a Masked Tweakable Block Cipher.
IACR Trans. Symmetric Cryptol., 2020

Modeling Soft Analytical Side-Channel Attacks from a Coding Theory Viewpoint.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

Side-Channel Countermeasures' Dissection and the Limits of Closed Source Security Evaluations.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

Mode-Level vs. Implementation-Level Physical Security in Symmetric Cryptography: A Practical Guide Through the Leakage-Resistance Jungle.
IACR Cryptol. ePrint Arch., 2020

On the Security of Off-the-Shelf Microcontrollers: Hardware Is Not Enough.
Proceedings of the Smart Card Research and Advanced Applications, 2020

2019
Multi-Tuple Leakage Detection and the Dependent Signal Issue.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

Leakage Certification Revisited: Bounding Model Errors in Side-Channel Security Evaluations.
IACR Cryptol. ePrint Arch., 2019

2018
Implementing Trojan-Resilient Hardware from (Mostly) Untrusted Components Designed by Colluding Manufacturers.
Proceedings of the 2018 Workshop on Attacks and Solutions in Hardware Security, 2018


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