Gaëtan Cassiers

Orcid: 0000-0001-5426-9345

Affiliations:
  • TU Graz, Austria
  • UCLouvain, ELEN, Louvain-la-Neuve, Belgium (former)


According to our database1, Gaëtan Cassiers authored at least 32 papers between 2018 and 2024.

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Timeline

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Bibliography

2024
Quantile: Quantifying Information Leakage.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

2023
SCALib: A Side-Channel Analysis Library.
J. Open Source Softw., June, 2023

Information Bounds and Convergence Rates for Side-Channel Security Evaluators.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

Prime-Field Masking in Hardware and its Soundness against Low-Noise SCA Attacks.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

Efficient Regression-Based Linear Discriminant Analysis for Side-Channel Security Evaluations Towards Analytical Attacks against 32-bit Implementations.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

Protecting Dilithium against Leakage Revisited Sensitivity Analysis and Improved Implementations.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

Kavach: Lightweight masking techniques for polynomial arithmetic in lattice-based cryptography.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

Randomness Generation for Secure Hardware Masking - Unrolled Trivium to the Rescue.
IACR Cryptol. ePrint Arch., 2023

Compress: Reducing Area and Latency of Masked Pipelined Circuits.
IACR Cryptol. ePrint Arch., 2023

Unifying Freedom and Separation for Tight Probing-Secure Composition.
IACR Cryptol. ePrint Arch., 2023

Towards Achieving Provable Side-Channel Security in Practice.
IACR Cryptol. ePrint Arch., 2023

2022
Composable and efficient masking schemes for side-channel secure implementations.
PhD thesis, 2022

Triplex: an Efficient and One-Pass Leakage-Resistant Mode of Operation.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Bitslicing Arithmetic/Boolean Masking Conversions for Fun and Profit with Application to Lattice-Based KEMs.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Analyzing the Leakage Resistance of the NIST's Lightweight Crypto Competition's Finalists.
IACR Cryptol. ePrint Arch., 2022

Unprotected and Masked Hardware Implementations of Spook v2.
IACR Cryptol. ePrint Arch., 2022

Handcrafting: Improving Automated Masking in Hardware with Manual Optimizations.
IACR Cryptol. ePrint Arch., 2022

Leveling Dilithium against Leakage: Revisited Sensitivity Analysis and Improved Implementations.
IACR Cryptol. ePrint Arch., 2022

2021
Provably Secure Hardware Masking in the Transition- and Glitch-Robust Probing Model: Better Safe than Sorry.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

Hardware Private Circuits: From Trivial Composition to Full Verification.
IEEE Trans. Computers, 2021

Towards Tight Random Probing Security.
IACR Cryptol. ePrint Arch., 2021

Give Me 5 Minutes: Attacking ASCAD with a Single Side-Channel Trace.
IACR Cryptol. ePrint Arch., 2021

How to fool a black box machine learning based side-channel security evaluation.
Cryptogr. Commun., 2021

2020
Spook: Sponge-Based Leakage-Resistant Authenticated Encryption with a Masked Tweakable Block Cipher.
IACR Trans. Symmetric Cryptol., 2020

Trivially and Efficiently Composing Masked Gadgets With Probe Isolating Non-Interference.
IEEE Trans. Inf. Forensics Secur., 2020

Efficient and Private Computations with Code-Based Masking.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

Packed Multiplication: How to Amortize the Cost of Side-channel Masking ?
IACR Cryptol. ePrint Arch., 2020

Mode-Level vs. Implementation-Level Physical Security in Symmetric Cryptography: A Practical Guide Through the Leakage-Resistance Jungle.
IACR Cryptol. ePrint Arch., 2020

2019
Towards Globally Optimized Masking: From Low Randomness to Low Noise Rate or Probe Isolating Multiplications with Reduced Randomness and Security against Horizontal Attacks.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

SpookChain: Chaining a Sponge-Based AEAD with Beyond-Birthday Security.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2019

maskVerif: Automated Verification of Higher-Order Masking in Presence of Physical Defaults.
Proceedings of the Computer Security - ESORICS 2019, 2019

2018
Improved Bitslice Masking: from Optimized Non-Interference to Probe Isolation.
IACR Cryptol. ePrint Arch., 2018


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