Thorben Moos

Orcid: 0000-0003-3809-9803

According to our database1, Thorben Moos authored at least 26 papers between 2016 and 2024.

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Bibliography

2024
Prime Masking vs. Faults - Exponential Security Amplification against Selected Classes of Attacks.
IACR Cryptol. ePrint Arch., 2024

2023
Prime-Field Masking in Hardware and its Soundness against Low-Noise SCA Attacks.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

Combined Private Circuits - Combined Security Refurbished.
IACR Cryptol. ePrint Arch., 2023

Randomness Generation for Secure Hardware Masking - Unrolled Trivium to the Rescue.
IACR Cryptol. ePrint Arch., 2023

Energy Consumption of Protected Cryptographic Hardware Cores - An Experimental Study.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2023

2022
Physical security for next generation CMOS ICs.
PhD thesis, 2022

Beware of Insufficient Redundancy An Experimental Evaluation of Code-based FI Countermeasures.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Red Team vs. Blue Team: A Real-World Hardware Trojan Detection Case Study Across Four Modern CMOS Technology Generations.
IACR Cryptol. ePrint Arch., 2022

Effective and Efficient Masking with Low Noise using Small-Mersenne-Prime Ciphers.
IACR Cryptol. ePrint Arch., 2022

2021
DL-LA: Deep Learning Leakage Assessment A modern roadmap for SCA evaluations.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

Countermeasures against Static Power Attacks - Comparing Exhaustive Logic Balancing and Other Protection Schemes in 28 nm CMOS -.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

Let's Take it Offline: Boosting Brute-Force Attacks on iPhone's User Authentication through SCA.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

The SPEEDY Family of Block Ciphers Engineering an Ultra Low-Latency Cipher from Gate Level for Secure Processor Architectures.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

Low-Latency Hardware Masking of PRINCE.
IACR Cryptol. ePrint Arch., 2021

2020
Static Power Side-Channel Analysis - An Investigation of Measurement Factors.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Side-Channel Hardware Trojan for Provably-Secure SCA-Protected Implementations.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Unrolled Cryptography on Silicon A Physical Security Analysis.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

The Risk of Outsourcing: Hidden SCA Trojans in Third-Party IP-Cores Threaten Cryptographic ICs.
IACR Cryptol. ePrint Arch., 2020

BSPL: Balanced Static Power Logic.
IACR Cryptol. ePrint Arch., 2020

PRINCEv2 - More Security for (Almost) No Overhead.
IACR Cryptol. ePrint Arch., 2020

2019
Glitch-Resistant Masking Revisited or Why Proofs in the Robust Probing Model are Needed.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

Static Power SCA of Sub-100 nm CMOS ASICs and the Insecurity of Masking Schemes in Low-Noise Environments.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

Exploring the Effect of Device Aging on Static Power Analysis Attacks.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

2018
Static Power Side-Channel Analysis - A Survey on Measurement Factors.
IACR Cryptol. ePrint Arch., 2018

2017
On the Easiness of Turning Higher-Order Leakages into First-Order.
IACR Cryptol. ePrint Arch., 2017

2016
Static Power Side-Channel Analysis of a Threshold Implementation Prototype Chip.
IACR Cryptol. ePrint Arch., 2016


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