Todor Mladenov

According to our database1, Todor Mladenov authored at least 15 papers between 2008 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Cryogenic CMOS for Qubit Control and Readout.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021
A Fully Integrated Cryo-CMOS SoC for State Manipulation, Readout, and High-Speed Gate Pulsing of Spin Qubits.
IEEE J. Solid State Circuits, 2021

A Fully Integrated Cryo-CMOS SoC for Qubit Control in Quantum Computers Capable of State Manipulation, Readout and High-Speed Gate Pulsing of Spin Qubits in Intel 22nm FFL FinFET Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2017
Radio frequency energy harvesting for wireless sensor networks.
Int. J. Distributed Sens. Networks, 2017

2013
Forward error correction with Raptor GF(2) and GF(256) codes on GPU.
IEEE Trans. Consumer Electron., 2013

Forward error correction with RaptorQ code on GPU.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Efficient GF(256) raptor code decoding for multimedia broadcast/multicast services and consumer terminals.
IEEE Trans. Consumer Electron., 2012

Decoding of Raptor codes on embedded systems.
Microprocess. Microsystems, 2012

Raptor Codes for P2P Streaming.
Proceedings of the 20th Euromicro International Conference on Parallel, 2012

2011
Implementation and Evaluation of Raptor Codes on Embedded Systems.
IEEE Trans. Computers, 2011

Efficient Incremental Raptor Decoding Over BEC for 3GPP MBMS and DVB IP-Datacast Services.
IEEE Trans. Broadcast., 2011

2010
MBMS raptor codes design trade-offs for IPTV.
IEEE Trans. Consumer Electron., 2010

Strategies for the design of raptor decoding in broadcast/multicast delivery systems.
IEEE Trans. Consumer Electron., 2010

Parallel scalable hardware architecture for hard Raptor decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2008
Implementation of reconfigurable SHA-2 hardware core.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008


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