Stefano Pellerano
According to our database1,
Stefano Pellerano
authored at least 60 papers
between 2003 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
22.3 A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET.
IEEE J. Solid State Circuits, December, 2023
IEEE J. Solid State Circuits, 2023
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A Fully Integrated 160-Gb/s D-Band Transmitter Achieving 1.1-pJ/b Efficiency in 22-nm FinFET.
IEEE J. Solid State Circuits, 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 2-to-2.48GHz Voltage-Interpolator-Based Fractional-N Type-I Sampling PLL in 22nm FinFET Assisting Fast Crystal Startup.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A Fully Integrated 160Gb/s D-Band Transmitter with 1.1 pJ/b Efficiency in 22nm FinFET Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
A Fully Integrated Cryo-CMOS SoC for State Manipulation, Readout, and High-Speed Gate Pulsing of Spin Qubits.
IEEE J. Solid State Circuits, 2021
A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-N MDLL in 22-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2021
A Reconfigurable Non-Uniform Power-Combining V-Band PA With +17.9 dBm P<sub>sat</sub> and 26.5% PAE in 16-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2021
A Fully Integrated Cryo-CMOS SoC for Qubit Control in Quantum Computers Capable of State Manipulation, Readout and High-Speed Gate Pulsing of Spin Qubits in Intel 22nm FFL FinFET Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
IEEE Trans. Circuits Syst., 2020
A Scalable Cryo-CMOS Controller for the Wideband Frequency-Multiplexed Control of Spin Qubits and Transmons.
IEEE J. Solid State Circuits, 2020
19.1 A Scalable Cryo-CMOS 2-to-20GHz Digitally Intensive Controller for 4×32 Frequency Multiplexed Spin Qubits/Transmons in 22nm FinFET Technology for Quantum Computers.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
25.5 A Self-Calibrated 1.2-to-3.8GHz 0.0052mm2 Synthesized Fractional-N MDLL Using a 2b Time-Period Comparator in 22nm FinFET CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
An $E$ -Band Power Amplifier With 26.3% PAE and 24-GHz Bandwidth in 22-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2019
A Scalable 71-to-76GHz 64-Element Phased-Array Transceiver Module with 2×2 Direct-Conversion IC in 22nm FinFET CMOS Technology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
A CMOS Wideband Current-Mode Digital Polar Power Amplifier With Built-In AM-PM Distortion Self-Compensation.
IEEE J. Solid State Circuits, 2018
802.11g/n Compliant Fully Integrated Wake-Up Receiver With -72-dBm Sensitivity in 14-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2018
IEEE Commun. Mag., 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2018
2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
13.8 A 24dBm 2-to-4.3GHz wideband digital Power Amplifier with built-in AM-PM distortion self-compensation.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
Proceedings of the 2015 IEEE International Conference on RFID, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2013
IEEE J. Solid State Circuits, 2013
2012
A 2.4-GHz 20-40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS.
IEEE J. Solid State Circuits, 2012
A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
A 12-element 60GHz CMOS phased array transmitter on LTCC package with integrated antennas.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
IEEE J. Solid State Circuits, 2010
A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving.
IEEE J. Solid State Circuits, 2010
2009
A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC-Based All-Digital Spur Calibration in 45-nm CMOS.
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A 2.5GHz, 6.9mW ΔΣ modulator with standard cell design in 45nm-LP CMOS using time-interleaving.
Proceedings of the 35th European Solid-State Circuits Conference, 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
IEEE J. Solid State Circuits, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the ESSCIRC 2008, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2006
A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process.
IEEE J. Solid State Circuits, 2006
A 5-GHz 108-Mb/s 2 $\times$2 MIMO Transceiver RFIC With Fully Integrated 20.5-dBm ${\rm P}_{\rm 1dB}$ Power Amplifiers in 90-nm CMOS.
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
A 5 GHz class-AB power amplifier in 90 nm CMOS with digitally-assisted AM-PM correction.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
PhD thesis, 2004
IEEE J. Solid State Circuits, 2004
2003
Proceedings of the ESSCIRC 2003, 2003