Tomasz Borejko

According to our database, Tomasz Borejko authored at least 21 papers between 2002 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

Erratum: Borejko, T., et al. NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor. Sensors 2020, 20, 1069.

Tomasz Borejko, Krzysztof Marcinek, Krzysztof Siwiec, Pawel Narczyk, Adam Borkowski, Igor Butryn, Arkadiusz W. Luczyk, Daniel Pietron, Maciej Plasota, Szymon Reszewicz, Lukasz Wiechowski, Witold A. Pleskacz

Sensors, 2020

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor.

Tomasz Borejko, Krzysztof Marcinek, Krzysztof Siwiec, Pawel Narczyk, Adam Borkowski, Igor Butryn, Arkadiusz W. Luczyk, Daniel Pietron, Maciej Plasota, Szymon Reszewicz, Lukasz Wiechowski, Witold A. Pleskacz

Sensors, 2020

2019

DC/DC Buck Converter with Build-in Tuned Sawtooth Wave Generator Using CMOS Technology.

Adam Borkowski, Tomasz Borejko, Witold A. Pleskacz

Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

2017

Importance of on-chip inductor modeling in radio frequency integrated circuits.

Daniel Pietron, Tomasz Borejko, Krzysztof Siwiec, Witold A. Pleskacz

Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017

2016

The integrated transmitter and receiver modules for pulse oximeter system.

Cezary Kolacinski, Andrzej Szymanski, Adam Jarosz, Ewa Kurjata-Pfitzner, Jerzy Wasowski, Tomasz Borejko, Krzysztof Siwiec, Witold A. Pleskacz

Proceedings of the 2016 MIXDES, 2016

Dedicated chip for pulse oximetry measurements.

Cezary Kolacinski, Jerzy Wasowski, Andrzej Szymanski, Adam Jarosz, Ewa Kurjata-Pfitzner, Tomasz Borejko, Krzysztof Siwiec, Witold A. Pleskacz

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

BioSoC: Highly integrated System-on-Chip for health monitoring.

Krzysztof Siwiec, Krzysztof Marcinek, Piotr Boguszewicz, Tomasz Borejko, Aleh Halauko, Adam Jarosz, Jakub Kopanski, Ewa Kurjata-Pfitzner, Pawel Narczyk, Maciej Plasota, Andrzej Wielgus, Witold A. Pleskacz

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015

A CMOS system-on-chip for physiological parameters acquisition, processing and monitoring.

Krzysztof Siwiec, Krzysztof Marcinek, Tomasz Borejko, Adam Jarosz, Jakub Kopanski, Ewa Kurjata-Pfitzner, Pawel Narczyk, Maciej Plasota, Andrzej Wielgus, Witold A. Pleskacz

Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

Low voltage LNA implementations in 28 nm FD-SOI technology for GNSS applications.

Aleh Halauko, Tomasz Borejko, Witold A. Pleskacz

Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

IF polyphase filter design and calibration with back-gate biasing in 28 nm FD-SOI technology.

Mariusz Derlecki, Tomasz Borejko, Witold A. Pleskacz

Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

2012

LC-VCO design automation tool for nanometer CMOS technology.

Krzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011

CAD tool for PLL Design.

Krzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

PVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applications.

Krzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

A resistorless current reference source for 65 nm CMOS technology with low sensitivity to process, supply voltage and temperature variations.

Michal Lukaszewicz, Tomasz Borejko, Witold A. Pleskacz

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010

A comparison of low voltage LNA architectures designed for multistandard GNSS in two 90 nm CMOS technologies.

Jacek Gradzki, Tomasz Borejko, Witold A. Pleskacz

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009

Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS.

Jacek Gradzki, Tomasz Borejko, Witold A. Pleskacz

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2008

DefSim: A Remote Laboratory for Studying Physical Defects in CMOS Digital Circuits.

Witold A. Pleskacz, Viera Stopjaková, Tomasz Borejko, Artur Jutman, Andrzej Walkanis

IEEE Trans. Ind. Electron., 2008

A Resistorless Voltage Reference Source for 90 nm CMOS Technology with Low Sensitivity to Process and Temperature Variations.

Tomasz Borejko, Witold A. Pleskacz

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology.

Marcin J. Beresinski, Tomasz Borejko, Witold A. Pleskacz, Viera Stopjaková

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2006

DefSim: CMOS Defects on Chip for Research and Education.

Witold A. Pleskacz, Tomasz Borejko, Andrzej Walkanis, Viera Stopjaková, Artur Jutman, Raimund Ubar

Proceedings of the 7th Latin American Test Workshop, 2006

2002

CMOS Standard Cells Characterization for IDDQ Testing.

Witold A. Pleskacz, Tomasz Borejko, Wieslaw Kuzmicz

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002