Tomoya Hirao

According to our database, Tomoya Hirao authored at least 5 papers between 2011 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

A software bridged data transfer on a FPGA cluster by using pipelining and InfiniBand verbs.

Takaaki Miyajima, Tomoya Hirao, Naoya Miyamoto, Jeongdo Son, Kentaro Sano

Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2019

2015

A flexible hardware barrier mechanism for many-core processors.

Takeshi Soga, Hiroshi Sasaki, Tomoya Hirao, Masaaki Kondo, Koji Inoue

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2013

A Prototype System for Many-Core Architecture SMYLEref with FPGA Evaluation Boards.

Son-Truong Nguyen, Masaaki Kondo, Tomoya Hirao, Koji Inoue

IEICE Trans. Inf. Syst., 2013

SMYLEref: A reference architecture for manycore-processor SoCs.

Masaaki Kondo, Son Truong Nguyen, Tomoya Hirao, Takeshi Soga, Hiroshi Sasaki, Koji Inoue

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2011

NSIM: An Interconnection Network Simulator for Extreme-Scale Parallel Computers.

Hideki Miwa, Ryutaro Susukita, Hidetomo Shibamura, Tomoya Hirao, Jun Maki, Makoto Yoshida, Takayuki Kando, Yuichiro Ajima, Ikuo Miyoshi, Toshiyuki Shimizu, Yuji Oinaga, Hisashige Ando, Yuichi Inadomi, Koji Inoue, Mutsumi Aoyagi, Kazuaki J. Murakami

IEICE Trans. Inf. Syst., 2011