Koji Inoue

Orcid: 0000-0003-3926-0646

According to our database1, Koji Inoue authored at least 186 papers between 1999 and 2024.

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Bibliography

2024
TinyEmergencyNet: a hardware-friendly ultra-lightweight deep learning model for aerial scene image classification.
J. Real Time Image Process., April, 2024

Character expression of a conversational robot for adapting to user personality.
Adv. Robotics, February, 2024

Multilingual Turn-taking Prediction Using Voice Activity Projection.
CoRR, 2024

SFQ counter-based precomputation for large-scale cryogenic VQE machines.
CoRR, 2024

Evaluation of a semi-autonomous attentive listening system with takeover prompting.
CoRR, 2024

Acknowledgment of Emotional States: Generating Validating Responses for Empathetic Dialogue.
CoRR, 2024

Real-time and Continuous Turn-taking Prediction Using Voice Activity Projection.
CoRR, 2024

An Analysis of User Behaviors for Objectively Evaluating Spoken Dialogue Systems.
CoRR, 2024

Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines.
IEEE Comput. Archit. Lett., 2024

2023
Effect of attentive listening robot on pleasure and arousal change in psychiatric daycare.
Adv. Robotics, November, 2023

Dual variational generative model and auxiliary retrieval for empathetic response generation by conversational robot.
Adv. Robotics, November, 2023

Character expression for spoken dialogue systems with semi-supervised learning using Variational Auto-Encoder.
Comput. Speech Lang., April, 2023

Empirical Power-performance Analysis of Layer-wise CNN Inference on Single Board Computers.
J. Inf. Process., 2023

Reasoning before Responding: Integrating Commonsense-based Causality Explanation for Empathetic Response Generation.
Proceedings of the 24th Meeting of the Special Interest Group on Discourse and Dialogue, 2023

Robotic Backchanneling in Online Conversation Facilitation: A Cross-Generational Study.
Proceedings of the 32nd IEEE International Conference on Robot and Human Interactive Communication, 2023

RealPersonaChat: A Realistic Persona Chat Corpus with Interlocutors' Own Personalities.
Proceedings of the 37th Pacific Asia Conference on Language, 2023

QIsim: Architecting 10+K Qubit QC Interfaces Toward Quantum Supremacy.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

Towards Objective Evaluation of Socially-Situated Conversational Robots: Assessing Human-Likeness through Multimodal User Behaviors.
Proceedings of the International Conference on Multimodal Interaction, 2023

CFChain: A Crowdfunding Platform that Supports Identity Authentication, Privacy Protection, and Efficient Audit.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2023

I Know Your Feelings Before You Do: Predicting Future Affective Reactions in Human-Computer Dialogue.
Proceedings of the Extended Abstracts of the 2023 CHI Conference on Human Factors in Computing Systems, 2023

Evaluating floating-point multipliers with opto-electrical hybrid circuits.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

Proceedings of the 21st Annual Workshop of the Australasian Language Technology Association.
Proceedings of the 21st Annual Workshop of the Australasian Language Technology Association, 2023

2022
Can a robot laugh with you?: Shared laughter generation for empathetic spoken dialogue.
Frontiers Robotics AI, 2022

An Edge Autonomous Lamp Control with Camera Feedback.
Proceedings of the 8th IEEE World Forum on Internet of Things, 2022

Simultaneous Job Interview System Using Multiple Semi-autonomous Agents.
Proceedings of the 23rd Annual Meeting of the Special Interest Group on Discourse and Dialogue, 2022

Q3DE: A fault-tolerant quantum computer architecture for multi-bit burst errors by cosmic rays.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Implementation of Edge-cloud Cooperative CNN Inference on an IoT Platform.
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

Design and Analysis of a Nano-photonic Processing Unit for Low-Latency Recurrent Neural Network Applications.
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

A Hybrid Opto-Electrical Floating-point Multiplier.
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

Design of Variable Bit-Width Arithmetic Unit Using Single Flux Quantum Device.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

XQsim: modeling cross-technology control processors for 10+K qubit quantum computers.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

Multimodal Persuasive Dialogue Corpus using Teleoperated Android.
Proceedings of the Interspeech 2022, 2022

Alzheimer's Dementia Detection through Spontaneous Dialogue with Proactive Robotic Listeners.
Proceedings of the ACM/IEEE International Conference on Human-Robot Interaction, 2022

Backchannel Generation Model for a Third Party Listener Agent.
Proceedings of the International Conference on Human-Agent Interaction, 2022

2021
Superconductor Computing for Neural Networks.
IEEE Micro, 2021

Intelligent Conversational Android ERICA Applied to Attentive Listening and Job Interview.
CoRR, 2021

Semi-autonomous avatar enabling unconstrained parallel conversations -seamless hybrid of WOZ and autonomous dialogue systems-.
Adv. Robotics, 2021

Fast Screen Content Coding in HEVC Using Machine Learning.
IEEE Access, 2021

A multi-party attentive listening robot which stimulates involvement from side participants.
Proceedings of the 22nd Annual Meeting of the Special Interest Group on Discourse and Dialogue, 2021

2020
Decision Tree Models and Early Splitting Termination in Screen Content Extension of High Efficiency Video Coding.
IEEE Access, 2020

32 GHz 6.5 mW Gate-Level-Pipelined 4-Bit Processor using Superconductor Single-Flux-Quantum Logic.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

An Attentive Listening System with Android ERICA: Comparison of Autonomous and WOZ Interactions.
Proceedings of the 21th Annual Meeting of the Special Interest Group on Discourse and Dialogue, 2020

SuperNPU: An Extremely Fast Neural Processing Unit Using Superconducting Logic Devices.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

A Character Expression Model Affecting Spoken Dialogue Behaviors.
Proceedings of the Conversational Dialogue Systems for the Next Decade, 2020

Response Generation to Out-of-Database Questions for Example-Based Dialogue Systems.
Proceedings of the Conversational Dialogue Systems for the Next Decade, 2020

Practical Error Modeling Toward Realistic NISQ Simulation.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

How Many Trials Do We Need for Reliable NISQ Computing?
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Semi-Supervised Learning for Character Expression of Spoken Dialogue Systems.
Proceedings of the Interspeech 2020, 2020

Prediction of Shared Laughter for Human-Robot Dialogue.
Proceedings of the Companion Publication of the 2020 International Conference on Multimodal Interaction, 2020

Job Interviewer Android with Elaborate Follow-up Question Generation.
Proceedings of the ICMI '20: International Conference on Multimodal Interaction, 2020

Enhancing a manycore-oriented compressed cache for GPGPU.
Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2020

Energy Efficient Runahead Execution on a Tightly Coupled Heterogeneous Core.
Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2020

2019
Radio Propagation Characteristics-based Spoofing Attack Prevention on Wireless Connected Devices.
J. Inf. Process., 2019

Critical Path Based Microarchitectural Bottleneck Analysis for Out-of-Order Execution.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

Expressing reactive emotion based on multimodal emotion recognition for natural conversation in human-robot interaction.
Adv. Robotics, 2019

Efficient Autoencoder-Based Human Body Communication Transceiver for WBAN.
IEEE Access, 2019

End-to-end Modeling for Selection of Utterance Constructional Units via System Internal States.
Proceedings of the Increasing Naturalness and Flexibility in Spoken Dialogue Interaction, 2019

Engagement-Based Adaptive Behaviors for Laboratory Guide in Human-Robot Dialogue.
Proceedings of the Increasing Naturalness and Flexibility in Spoken Dialogue Interaction, 2019

A Job Interview Dialogue System with Autonomous Android ERICA.
Proceedings of the Increasing Naturalness and Flexibility in Spoken Dialogue Interaction, 2019

A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Turn-Taking Prediction Based on Detection of Transition Relevance Place.
Proceedings of the Interspeech 2019, 2019

Smooth Turn-taking by a Robot Using an Online Continuous Model to Generate Turn-taking Cues.
Proceedings of the International Conference on Multimodal Interaction, 2019

An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor.
Proceedings of the International Conference on Field-Programmable Technology, 2019

Evaluating the Impact of Energy Efficient Networks on HPC Workloads.
Proceedings of the 26th IEEE International Conference on High Performance Computing, 2019

2018
Engagement Recognition based on Multimodal Behaviors for Human-Robot Dialogue.
PhD thesis, 2018

Automatic Arrival Time Detection for Earthquakes Based on Stacked Denoising Autoencoder.
IEEE Geosci. Remote. Sens. Lett., 2018

An Integrated Nanophotonic Parallel Adder.
ACM J. Emerg. Technol. Comput. Syst., 2018

Parallel Precomputation with Input Value Prediction for Model Predictive Control Systems.
IEICE Trans. Inf. Syst., 2018

Towards Ultra-High-Speed Cryogenic Single-Flux-Quantum Computing.
IEICE Trans. Electron., 2018

Real-Time Frame-Rate Control for Energy-Efficient On-Line Object Tracking.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Evaluating Energy-Efficiency of DRAM Channel Interleaving Schemes for Multithreaded Programs.
IEICE Trans. Inf. Syst., 2018

VMOR: Microarchitectural Support for Operand Access in an Interpreter.
IEEE Comput. Archit. Lett., 2018

Generating Fillers Based on Dialog Act Pairs for Smooth Turn-Taking by Humanoid Robot.
Proceedings of the 9th International Workshop on Spoken Dialogue System Technology, 2018

Latent Character Model for Engagement Recognition Based on Multimodal Behaviors.
Proceedings of the 9th International Workshop on Spoken Dialogue System Technology, 2018

Analyzing Resource Trade-offs in Hardware Overprovisioned Supercomputers.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium, 2018

Engagement Recognition in Spoken Dialogue via Neural Network by Aggregating Different Annotators' Models.
Proceedings of the Interspeech 2018, 2018

Prediction of Turn-taking Using Multitask Learning with Prediction of Backchannels and Fillers.
Proceedings of the Interspeech 2018, 2018

Evaluation of Real-time Deep Learning Turn-taking Models for Multiple Dialogue Scenarios.
Proceedings of the 2018 on International Conference on Multimodal Interaction, 2018

Audio-Visual Conversation Analysis by Smart Posterboard and Humanoid Robot.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

An End-to-End Approach to Joint Social Signal Detection and Automatic Speech Recognition.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

Performance Analysis of CPU and DRAM Power Constrained Systems with Magnetohydrodynamic Simulation Code.
Proceedings of the 20th IEEE International Conference on High Performance Computing and Communications; 16th IEEE International Conference on Smart City; 4th IEEE International Conference on Data Science and Systems, 2018

Panel discussions: "Challenges to the scaling limits: How can we achieve sustainable power-performance improvements?".
Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018

Dialogue Behavior Control Model for Expressing a Character of Humanoid Robots.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2018

Autoencoder based Features Extraction for Automatic Classification of Earthquakes and Explosions.
Proceedings of the 17th IEEE/ACIS International Conference on Computer and Information Science, 2018

2017
Dependence Graph Model for Accurate Critical Path Analysis on Out-of-Order Processors.
J. Inf. Process., 2017

Detection of social signals for recognizing engagement in human-robot interaction.
CoRR, 2017

Enhanced Dependence Graph Model for Critical Path Analysis on Modern Out-of-Order Processors.
IEEE Comput. Archit. Lett., 2017

Attentive listening system with backchanneling, response generation and flexible turn-taking.
Proceedings of the 18th Annual SIGdial Meeting on Discourse and Dialogue, 2017

A Conversational Dialogue Manager for the Humanoid Robot ERICA.
Proceedings of the Advanced Social Interaction with Agents, 2017

Production Hardware Overprovisioning: Real-World Performance Optimization Using an Extensible Power-Aware Resource Management Framework.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

Social Signal Detection in Spontaneous Dialogue Using Bidirectional LSTM-CTC.
Proceedings of the Interspeech 2017, 2017

CPCI Stack: Metric for Accurate Bottleneck Analysis on OoO Microprocessors.
Proceedings of the Fifth International Symposium on Computing and Networking, 2017

Wireless Spoofing-Attack Prevention Using Radio-Propagation Characteristics.
Proceedings of the 15th IEEE Intl Conf on Dependable, 2017

Emotion recognition by combining prosody and sentiment analysis for expressing reactive emotion by humanoid robot.
Proceedings of the 2017 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2017

2016
Talking with ERICA, an autonomous android.
Proceedings of the SIGDIAL 2016 Conference, 2016

Power-Efficient Breadth-First Search with DRAM Row Buffer Locality-Aware Address Mapping.
Proceedings of the 2016 High Performance Graph Data Management and Processing Workshop, 2016

An integrated optical parallel adder as a first step towards light speed data processing.
Proceedings of the International SoC Design Conference, 2016

Single-flux-quantum cache memory architecture.
Proceedings of the International SoC Design Conference, 2016

Prediction and Generation of Backchannel Form for Attentive Listening Systems.
Proceedings of the Interspeech 2016, 2016

Multimodal interaction with the autonomous Android ERICA.
Proceedings of the 18th ACM International Conference on Multimodal Interaction, 2016

Annotation and analysis of listener's engagement based on multi-modal behaviors.
Proceedings of the Workshop on Multimodal Analyses enabling Artificial Agents in Human-Machine Interaction, 2016

Prediction of ice-breaking between participants using prosodic features in the first meeting dialogue.
Proceedings of the 2nd Workshop on Advancements in Social Signal Processing for Multimodal Interaction, 2016

From FLOPS to BYTES: disruptive change in high-performance computing towards the post-moore era.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Evaluating the impacts of code-level performance tunings on power efficiency.
Proceedings of the 2016 IEEE International Conference on Big Data (IEEE BigData 2016), 2016

2015
Analyzing and mitigating the impact of manufacturing variability in power-constrained supercomputing.
Proceedings of the International Conference for High Performance Computing, 2015

Characterization and cross-platform analysis of high-throughput accelerators.
Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

Enhanced speaker diarization with detection of backchannels using eye-gaze information in poster conversations.
Proceedings of the INTERSPEECH 2015, 2015

A flexible hardware barrier mechanism for many-core processors.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Speech-based human-robot interaction robust to acoustic reflections in real environment.
Proceedings of the 2014 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2014

Power and Performance Characterization and Modeling of GPU-Accelerated Systems.
Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014

Speaker diarization using eye-gaze information in multi-party conversations.
Proceedings of the INTERSPEECH 2014, 2014

Power-capped DVFS and thread allocation with ANN models on modern NUMA systems.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Power Consumption Evaluation of an MHD Simulation with CPU Power Capping.
Proceedings of the 14th IEEE/ACM International Symposium on Cluster, 2014

Speaker diarization based on audio-visual integration for smart posterboard.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2014

2013
A Prototype System for Many-Core Architecture SMYLEref with FPGA Evaluation Boards.
IEICE Trans. Inf. Syst., 2013

Static Mapping of Multiple Data-Parallel Applications on Embedded Many-Core SoCs.
IEICE Trans. Inf. Syst., 2013

An Inter-Prediction Method Using Sparse Representation for High Efficiency Video Coding.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Many-core acceleration for model predictive control systems.
Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, 2013

Power and performance of GPU-accelerated systems: A closer look.
Proceedings of the IEEE International Symposium on Workload Characterization, 2013

Hybrid compile and run-time memory management for a 3D-stacked reconfigurable accelerator.
Proceedings of the International Conference on Compilers, 2013

Line sharing cache: Exploring cache capacity with frequent line value locality.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

SMYLEref: A reference architecture for manycore-processor SoCs.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

SMYLE Project: Toward high-performance, low-power computing on manycore-processor SoCs.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Coordinated power-performance optimization in manycores.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012
Improving performance and energy efficiency of embedded processors via post-fabrication instruction set customization.
J. Supercomput., 2012

A Linear Manifold Color Descriptor for Medicine Package Recognition.
IEICE Trans. Inf. Syst., 2012

Power and Performance Analysis of GPU-Accelerated Systems.
Proceedings of the 2012 Workshop on Power-Aware Computing Systems, HotPower'12, 2012

Task mapping techniques for embedded many-core SoCs.
Proceedings of the International SoC Design Conference, 2012

Local intensity compensation using sparse representation.
Proceedings of the 21st International Conference on Pattern Recognition, 2012

A Three-Dimensional Integrated Accelerator.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Scalability-based manycore partitioning.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
A design scheme for a reconfigurable accelerator implemented by single-flux quantum circuits.
J. Syst. Archit., 2011

NSIM: An Interconnection Network Simulator for Extreme-Scale Parallel Computers.
IEICE Trans. Inf. Syst., 2011

Illumination-robust face recognition via sparse representation.
Proceedings of the 2011 IEEE Visual Communications and Image Processing, 2011

Real time 2D-DWT of JPEG 2000 for Digital Cinema using CUDA 4.0.
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2011

Routing architecture and algorithms for a superconductivity circuits-based computing hardware.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

A thermal-aware mapping algorithm for reducing peak temperature of an accelerator deployed in a 3D stack.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Performance evaluation of 3D stacked multi-core processors with temperature consideration.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Reducing On-Chip DRAM Energy via Data Transfer Size Optimization.
IEICE Trans. Electron., 2009

Rapid Design Space Exploration of a Reconfigurable Instruction-Set Processor.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Performance balancing: software-based on-chip memory management for effective CMP executions.
Proceedings of the 10th workshop on MEmory performance, 2009

A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
An architecture framework for an adaptive extensible processor.
J. Supercomput., 2008

Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum Circuits.
IEICE Trans. Electron., 2008

A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom Instructions.
IEICE Trans. Electron., 2008

Temperature-Aware Configurable Cache to Reduce Energy in Embedded Systems.
IEICE Trans. Electron., 2008

A gravity-directed temporal partitioning approach.
IEICE Electron. Express, 2008

Performance prediction of large-scale parallell system and application using macro-level simulation.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2008

Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Improved Policies for Drowsy Caches in Embedded Processors.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Design space exploration for a coarse grain accelerator.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Analyzing the impact of data prefetching on Chip MultiProcessors.
Proceedings of the 13th Asia-Pacific Computer Systems Architecture Conference, 2008

2007
A Next-Generation Enterprise Server System with Advanced Cache Coherence Chips.
IEICE Trans. Electron., 2007

Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs.
IEICE Trans. Inf. Syst., 2007

Multi-physics Extension of OpenFMO Framework
CoRR, 2007

Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator.
Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007

The effect of temperature on cache size tuning for low energy embedded systems.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems.
Proceedings of the 2007 International Conference on Embedded Systems & Applications, 2007

2006
Return Address Protection on Cache Memories.
IEICE Trans. Electron., 2006

Lock and Unlock: A Data Management Algorithm for A Security-Aware Cache.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Supporting A Dynamic Program Signature: An Intrusion Detection Framework for Microprocessors.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2006

An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

2005
Energy-security tradeoff in a secure cache architecture against buffer overflow attacks.
SIGARCH Comput. Archit. News, 2005

Adaptive Mode Control for Low-Power Caches Based on Way-Prediction Accuracy.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

A Cost Effective Spacial Redundancy with Data-Path Partitioning.
Proceedings of the Third International Conference on Information Technology and Applications (ICITA 2005), 2005

2004
A low-power I-cache design with tag-comparison reuse.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004

2003
Pipelined delay-sum architecture based on bucket-brigade devices for on-chip ultrasound beamforming.
IEEE J. Solid State Circuits, 2003

Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Reducing Access Count to Register-Files through Operand Reuse.
Proceedings of the Advances in Computer Systems Architecture, 2003

2002
Register File Energy Reduction by Operand Data Reuse.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints.
Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002

Reducing energy consumption of video memory by bit-width compression.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

A history-based I-cache for low-energy multimedia applications.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

A Low Energy Set-Associative I-Cache with Extended BTB.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Multiplier energy reduction through bypassing of partial products.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

Reducing power consumption of instruction ROMs by exploiting instruction frequency.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2000
Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems.
Proceedings of the Intelligent Memory Systems, Second International Workshop, 2000

1999
MOE: A Special-Purpose Parallel Computer for High-Speed, Large-Scale Molecular Orbital Calculation.
Proceedings of the ACM/IEEE Conference on Supercomputing, 1999

Way-predicting set-associative cache for high performance and low energy consumption.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs.
Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999


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