Masaaki Kondo

According to our database1, Masaaki Kondo authored at least 65 papers between 2000 and 2019.

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Bibliography

2019
A Neural Network Based On-device Learning Anomaly Detector for Edge Devices.
CoRR, 2019

Generation High resolution 3D model from natural language by Generative Adversarial Network.
CoRR, 2019

2018
A new device for fiducial registration of image-guided navigation system for liver RFA.
Int. J. Comput. Assist. Radiol. Surg., 2018

A Power Management Framework with Simple DSL for Automatic Power-Performance Optimization on Power-Constrained HPC Systems.
Proceedings of the Supercomputing Frontiers - 4th Asian Conference, 2018

Analyzing Resource Trade-offs in Hardware Overprovisioned Supercomputers.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium, 2018

OS-ELM-FPGA: An FPGA-Based Online Sequential Unsupervised Anomaly Detector.
Proceedings of the Euro-Par 2018: Parallel Processing Workshops, 2018

2017
Adaptive Power Management in Solar Energy Harvesting Sensor Node Using Reinforcement Learning.
ACM Trans. Embedded Comput. Syst., 2017

The Design and Implementation of Scalable Deep Neural Network Accelerator Cores.
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

Scalable deep neural network accelerator cores with cubic integration using through chip interface.
Proceedings of the International SoC Design Conference, 2017

Building block multi-chip systems using inductive coupling through chip interface.
Proceedings of the International SoC Design Conference, 2017

Production Hardware Overprovisioning: Real-World Performance Optimization Using an Extensible Power-Aware Resource Management Framework.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

Cooling-Aware Job Scheduling and Node Allocation for Overprovisioned HPC Systems.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

2016
An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications.
IEICE Transactions, 2016

A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip.
IEICE Transactions, 2016

Opportunistic circuit-switching for energy efficient on-chip networks.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Demand-Aware Power Management for Power-Constrained HPC Systems.
Proceedings of the IEEE/ACM 16th International Symposium on Cluster, 2016

2015
A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units.
IEICE Transactions, 2015

Analyzing and mitigating the impact of manufacturing variability in power-constrained supercomputing.
Proceedings of the International Conference for High Performance Computing, 2015

Runtime multi-optimizations for energy efficient on-chip interconnections1.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

A flexible hardware barrier mechanism for many-core processors.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014

Design and evaluation of fine-grained power-gating for embedded microprocessors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface.
IEEE Micro, 2013

A Prototype System for Many-Core Architecture SMYLEref with FPGA Evaluation Boards.
IEICE Transactions, 2013

Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design.
IEICE Transactions, 2013

Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface.
Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013

SMYLEref: A reference architecture for manycore-processor SoCs.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Geyser.
Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

FLAT: a GPU programming framework to provide embedded MPI.
Proceedings of the 5th Annual Workshop on General Purpose Processing with Graphics Processing Units, 2012

2011
Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips.
IEEE Micro, 2011

Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units.
IPSJ Trans. System LSI Design Methodology, 2011

Cool Mega-Array: A highly energy efficient reconfigurable accelerator.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator.
Proceedings of the 2011 IEEE Symposium on Low-Power and High-Speed Chips, 2011

Geyser-2: The second prototype CPU with fine-grained run-time power gating.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Adaptive power gating for function units in a microprocessor.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping.
IEEE Trans. VLSI Syst., 2009

Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Cooperative shared resource access control for low-power chip multiprocessors.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Power-performance modeling of heterogeneous cluster-based web servers.
Proceedings of the 2009 10th IEEE/ACM International Conference on Grid Computing, 2009

2008
A fine-grain dynamic sleep control scheme in MIPS R3000.
Proceedings of the 26th International Conference on Computer Design, 2008

2007
Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS.
SIGARCH Computer Architecture News, 2007

A High Performance Cluster System Design by Adaptie Power Control.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Power reduction of chip multi-processors using shared resource control cooperating with DVFS.
Proceedings of the 25th International Conference on Computer Design, 2007

Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

An intra-task dvfs technique based on statistical analysis of hardware events.
Proceedings of the 4th Conference on Computing Frontiers, 2007

2006
Design Method of High Performance and Low Power Functional Units Considering Delay Variations.
IEICE Transactions, 2006

Energy-efficient dynamic instruction scheduling logic through instruction grouping.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

2005
Dynamic Instruction Cascading on GALS Microprocessors.
Proceedings of the Integrated Circuit and System Design, 2005

Empirical Study for Optimization of Power-Performance with On-Chip Memory.
Proceedings of the High-Performance Computing - 6th International Symposium, 2005

A Small, Fast and Low-Power Register File by Bit-Partitioning.
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

2004
SCIMA-SMP: on-chip memory processor architecture for SMP.
Proceedings of the 3rd Workshop on Memory Performance Issues, 2004

Skewed Checkpointing for Tolerating Multi-Node Failures.
Proceedings of the 23rd International Symposium on Reliable Distributed Systems (SRDS 2004), 2004

Dynamic Processor Throttling for Power Efficient Computations.
Proceedings of the Power-Aware Computer Systems, 4th International Workshop, 2004

Data Movement Optimization for Software-Controlled On-Chip Memory.
Proceedings of the 8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 2004

2002
Software-controlled on-chip memory for high-performance and low-power computing.
SIGARCH Computer Architecture News, 2002

Cache Line Impact on 3D PDE Solvers.
Proceedings of the High Performance Computing, 4th International Symposium, 2002

Design and evaluation of high performance microprocessor with reconfigurable on-chip memory.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2000
Software Controlled Reconfigurable On-Chip Memory for High Performance Computing.
Proceedings of the Intelligent Memory Systems, Second International Workshop, 2000

SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

An acoustic measure for predicting recognition performance degradation.
Proceedings of the IEEE International Conference on Acoustics, 2000


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