Toshiaki Kitamura

According to our database1, Toshiaki Kitamura authored at least 15 papers between 1980 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2021
OSCAR Parallelizing and Power Reducing Compiler and API for Heterogeneous Multicores : (Invited Paper).
Proceedings of the IEEE/ACM Programming Environments for Heterogeneous Computing, 2021

2020
A Transmission-Line-Based Cochlear Standing Wave Model To Elucidate Mechanism of Human Auditory System.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020

2019
Cascaded DMA Controller for Speedup of Indirect Memory Access in Irregular Applications.
Proceedings of the 9th IEEE/ACM Workshop on Irregular Applications: Architectures and Algorithms, 2019

Possibility of Acoustic Resonance in Hair Cells in Human's Auditory System.
Proceedings of the 41st Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2019

2012
FDTD Analysis of a Near-Field Optical Disk with a Ridged-Square Nano-Aperture.
IEICE Trans. Electron., 2012

2010
Numerical Analysis of DWDD Disk with Control Layer.
IEICE Trans. Electron., 2010

Analysis of a Near-Field Optical Disk with an Acute-Edged Metallic Nano-Aperture.
IEICE Trans. Electron., 2010

2008
Evaluation of low-energy and high-performance processor using variable stages pipeline technique.
IET Comput. Digit. Tech., 2008

2007
A MATLAB-Based Code Generator for Parallel Sparse Matrix Computations Utilizing PSBLAS.
IEICE Trans. Inf. Syst., 2007

2004
A MATLAB-Based Code Generator for Sparse Matrix Computations.
Proceedings of the Programming Languages and Systems: Second Asian Symposium, 2004

2001
A high-speed dynamic instruction scheduling scheme for superscalar processors.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

1995
Scalar Processor of the VPP500 Parallel Supercomputer.
Proceedings of the 9th international conference on Supercomputing, 1995

1983
A User-Microprogrammable, Local Host Computer With Low-Level Parallelism
Proceedings of the 10th Annual Symposium on Computer Architecture, 1983, 1983

1980
Performance evaluation and improvement of a dynamically microprogrammable computer with low-level parallelism.
Proceedings of the 13th annual workshop on Microprogramming, 1980

Performance Evaluation and Improvement of a Dynamically Microprogrammable Computer with Low-Level Parallelism.
Proceedings of the Information Processing, Proceedings of the 8th IFIP Congress 1980, Tokyo, Japan - October 6-9, 1980 and Melbourne, Australia, 1980


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