Masahiro Goshima

According to our database, Masahiro Goshima authored at least 35 papers between 1993 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Out-of-Step Pipeline for Gather/Scatter Instructions.

Yi Ge, Katsuhiro Yoda, Makiko Ito, Toshiyuki Ichiba, Takahide Yoshikawa, Ryota Shioya, Masahiro Goshima

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2019

An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor.

Susumu Mashimo, Koji Inoue, Ryota Shioya, Akifumi Fujita, Reoma Matsuo, Seiya Akaki, Akifumi Fukuda, Toru Koizumi, Junichiro Kadomoto, Hidetsugu Irie, Masahiro Goshima

Proceedings of the International Conference on Field-Programmable Technology, 2019

2018

Bank-Aware Instruction Scheduler for a Multibanked Register File.

Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai

J. Inf. Process., 2018

Isolation-Safe Speculative Access Control for Hardware Transactional Memory.

Tomoki Tajimi, Masaki Hayashi, Yuki Futamase, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

An Analysis and a Solution of False Conflicts for Hardware Transactional Memory.

Yuki Futamase, Masaki Hayashi, Tomoki Tajimi, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Application of Timing Fault Detection to Rocket Core on FPGA.

Ushio Jimbo, Ryota Shioya, Masahiro Goshima

Proceedings of the Sixth International Symposium on Computing and Networking, 2018

A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode.

Yasumasa Chidai, Kojiro Izuoka, Ryota Shioya, Masahiro Goshima, Hideki Ando

Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018

2017

Skewed Multistaged Multibanked Register File for Area and Energy Efficiency.

Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai

IEICE Trans. Inf. Syst., 2017

Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology.

Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai

IEICE Trans. Electron., 2017

Applying Razor Flip-Flops to SRAM Read Circuits.

Ushio Jimbo, Junji Yamada, Ryota Shioya, Masahiro Goshima

IEICE Trans. Electron., 2017

Initial study of a phase-aware scheduling for hardware transactional memory.

Tomoki Tajimi, Anju Hirota, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura

Proceedings of the IEEE Pacific Rim Conference on Communications, 2017

2016

FXA: Executing Instructions in Front-End for Energy Efficiency.

Ryota Shioya, Ryo Takami, Masahiro Goshima, Hideki Ando

IEICE Trans. Inf. Syst., 2016

An Inductive Method to Select Simulation Points.

Minseong Choi, Takashi Fukuda, Masahiro Goshima, Shuichi Sakai

IEICE Trans. Inf. Syst., 2016

2015

Address Order Violation Detection with Parallel Counting Bloom Filters.

Naruki Kurata, Ryota Shioya, Masahiro Goshima, Shuichi Sakai

IEICE Trans. Electron., 2015

2014

A Front-End Execution Architecture for High Energy Efficiency.

Ryota Shioya, Masahiro Goshima, Hideki Ando

Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

A cloud architecture for protecting guest's information from malicious operators with memory management.

Koki Murakami, Tsuyoshi Yamada, Rie Shigetomi Yamaguchi, Masahiro Goshima, Shuichi Sakai

Proceedings of the Fourth ACM Conference on Data and Application Security and Privacy, 2014

2013

Register Indirect Jump Target Forwarding.

Ryota Shioya, Naruki Kurata, Takashi Toyoshima, Masahiro Goshima, Shuichi Sakai

IEICE Trans. Inf. Syst., 2013

2011

Low-Overhead Architecture for Security Tag.

Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, Shuichi Sakai

IEICE Trans. Inf. Syst., 2011

2010

Register Cache System Not for Latency Reduction Purpose.

Ryota Shioya, Kazuo Horio, Masahiro Goshima, Shuichi Sakai

Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

2009

String-Wise Information Flow Tracking against Script Injection Attacks.

Kunbo Li, Ryota Shioya, Masahiro Goshima, Shuichi Sakai

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

2008

Ultra Dependable Processor.

Shuichi Sakai, Masahiro Goshima, Hidetsugu Irie

IEICE Trans. Electron., 2008

Low-Complexity Bypass Network Using Small RAM.

Shinobu Miwa, Hironori Ichibayashi, Hidetsugu Irie, Masahiro Goshima, Hironori Nakajo, Shinji Tomita

Proceedings of the 2008 International Conference on Computer Design, 2008

2007

Preventing timing errors on register writes: mechanisms of detections and recoveries.

Hidetsugu Irie, Ken Sugimoto, Masahiro Goshima, Shuichi Sakai

SIGARCH Comput. Archit. News, 2007

Utilization of SECDED for soft error and variation-induced defect tolerance in caches.

Luong Dinh Hung, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Base Address Recognition with Data Flow Tracking for Injection Attack Detection.

Satoshi Katsunuma, Hiroyuki Kurita, Ryota Shioya, Kazuto Shimizu, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai

Proceedings of the 12th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2006), 2006

SEVA: A Soft-Error- and Variation-Aware Cache Architecture.

Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai

Proceedings of the 12th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2006), 2006

2005

Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag.

Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2004

Implementation of Cell-Projection Parallel Volume Rendering with Dynamic Load Balancing.

Motohiro Takayama, Yuki Shinomoto, Masahiro Goshima, Shin-ichiro Mori, Yasuhiko Nakashima, Shinji Tomita

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2004

2001

A high-speed dynamic instruction scheduling scheme for superscalar processors.

Masahiro Goshima, Kengo Nishino, Toshiaki Kitamura, Yasuhiko Nakashima, Shinji Tomita, Shin-ichiro Mori

Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

1999

A Technique to Eliminate Redundant Inter-Processor Communication on Parallelizing Compiler TINPAR.

Atsushi Kubota, Shogo Tatsumi, Toshihiko Tanaka, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita

Int. J. Parallel Program., 1999

1998

Optimized Code Generation for Heterogeneous Computing Environment using Parallelizing Compiler TINPAR.

Shin-ya Goto, Atsushi Kubota, Toshihiko Tanaka, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita

Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, 1998

1997

Improvement of message communication in concurrent logic language.

Kazuhiko Ohno, Masahiko Ikawa, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita, Masahiro Goshima

Proceedings of the 2nd International Workshop on Parallel Symbolic Computation, 1997

Efficient Goal Scheduling in Concurrent Logic Language using Type-Based Dependency Analysis.

Kazuhiko Ohno, Masahiko Ikawa, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita

Proceedings of the Advances in Computing Science, 1997

1995

A proposal of self-cleanup cache.

Shin-ichiro Mori, Masahiro Goshima, Hiroshi Nakashima, Shinji Tomita

Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, 1995

1993

A distributed shared memory multiprocessor ASURA: memory and cache architecture.

Shin-ichiro Mori, Hideki Saito, Masahiro Goshima, Mamoru Yanagihara, Takashi Tanaka, David Fraser, Kazuki Joe, Hiroyuki Nitta, Shinji Tomita

Proceedings of the Proceedings Supercomputing '93, 1993