Tetsuo Hironaka
According to our database1,
Tetsuo Hironaka
authored at least 30 papers
between 1992 and 2021.
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Bibliography
2021
J. Inf. Process., 2021
2019
Easy-going Development of Event-Driven Applications by Iterating a Search-Select-Superpose Loop.
J. Inf. Process., 2019
Resolving Ambiguous Types in Haskell by Checking Uniqueness of Type Variable Assignments under Type Class Constraints.
J. Inf. Process., 2019
SAIFU: Supporting Program Understanding by Automatic Indexing of Functionalities in Source Code.
Int. J. Networked Distributed Comput., 2019
Efficient Searching for Essential API Member Sets based on Inclusion Relation Extraction.
Int. J. Networked Distributed Comput., 2019
Supporting Program Understanding by Automatic Indexing of Functionalities in Source Code.
Proceedings of the 17th IEEE International Conference on Software Engineering Research, 2019
Proceedings of the 17th IEEE International Conference on Software Engineering Research, 2019
Proceedings of the 2019 IEEE International Conference on Software Maintenance and Evolution, 2019
2018
Proceedings of the Programming Languages and Systems - 16th Asian Symposium, 2018
2015
2012
A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks.
IEICE Trans. Inf. Syst., 2012
2011
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
Design consideration for reconfigurable processor DS-HIE - Trade-off between performance and chip area.
Proceedings of the International SoC Design Conference, 2011
2010
Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor.
Proceedings of the Reconfigurable Computing: Architectures, 2010
2008
Evaluation of low-energy and high-performance processor using variable stages pipeline technique.
IET Comput. Digit. Tech., 2008
Evaluation of compact high-throughput reconfigurable architecture based on bit-serial computation.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008
Exploring compact design on high throughput coarse grained reconfigurable architectures.
Proceedings of the FPL 2008, 2008
2007
4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words.
IEICE Trans. Electron., 2007
2006
Syst. Comput. Jpn., 2006
Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
Syst. Comput. Jpn., 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
A coarse-grained reconfigurable architecture with low cost configuration data compression mechanism.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003
2002
A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model.
Proceedings of the Field-Programmable Logic and Applications, 2002
2000
Performance Improvements of Thakore's Algorithm with Speculative Execution Technique and Dynamic Task Scheduling.
Informatica (Slovenia), 2000
Prototype microprocessor LSI with scheduling support hardware for operating system on multiprocessor system.
Proceedings of ASP-DAC 2000, 2000
1993
Proceedings of the 7th international conference on Supercomputing, 1993
1992
Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture.
Proceedings of the 6th international conference on Supercomputing, 1992