Tsai-Kan Chien

According to our database, Tsai-Kan Chien authored at least 5 papers between 2016 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2018

Highly Reliable Two-Step Charge-Pump Read Scheme for 1.5 F²/Bit Nonlinear Sub-Teraohm 0TNR Vertical ReRAM.

Tsai-Kan Chien, Lih-Yih Chiou, Chi-Shian Chang, Jing-Yu Huang, Chung-Han Wu, Heng-Yuan Lee, Shyh-Shyuan Sheu

IEEE Trans. Circuits Syst. II Express Briefs, 2018

2017

Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches.

Tsai-Kan Chien, Lih-Yih Chiou, Yi-Sung Tsou, Shyh-Shyuan Sheu, Pei-Hua Wang, Ming-Jinn Tsai, Chih-I Wu

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

2016

Low-Power MCU With Embedded ReRAM Buffers as Sensor Hub for IoT Applications.

Tsai-Kan Chien, Lih-Yih Chiou, Shyh-Shyuan Sheu, Jing-Cian Lin, Chang-Chia Lee, Tzu-Kun Ku, Ming-Jinn Tsai, Chih-I Wu

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

A low store energy and robust ReRAM-based flip-flop for normally off microprocessors.

Tsai-Kan Chien, Lih-Yih Chiou, Yao-Chun Chuang, Shyh-Shyuan Sheu, Heng-Yuan Li, Pei-Hua Wang, Tzu-Kun Ku, Ming-Jinn Tsai, Chih-I Wu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Memory access algorithm for low energy CPU/GPU heterogeneous systems with hybrid DRAM/NVM memory architecture.

Tsai-Kan Chien, Lih-Yih Chiou, Chieh-Wen Cheng, Shyh-Shyuan Sheu, Pei-Hua Wang, Ming-Jinn Tsai, Chih-I Wu

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016