Heng-Yuan Lee
According to our database1,
Heng-Yuan Lee
authored at least 13 papers
between 2011 and 2020.
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Bibliography
2020
15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
NV-BNN: An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI Edge.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
Highly Reliable Two-Step Charge-Pump Read Scheme for 1.5 F<sup>2</sup>/Bit Nonlinear Sub-Teraohm 0TNR Vertical ReRAM.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
2017
Analyzing inference robustness of RRAM synaptic array in low-precision neural network.
Proceedings of the 47th European Solid-State Device Research Conference, 2017
2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
2014
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes.
IEEE J. Solid State Circuits, 2013
2012
2011
IEEE Des. Test Comput., 2011
A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011