Ming-Jinn Tsai
According to our database1,
Ming-Jinn Tsai
authored at least 17 papers
between 2010 and 2017.
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Bibliography
2017
Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
A low store energy and robust ReRAM-based flip-flop for normally off microprocessors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Memory access algorithm for low energy CPU/GPU heterogeneous systems with hybrid DRAM/NVM memory architecture.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Set-Triggered-Parallel-Reset Memristor Logic for High-Density Heterogeneous-Integration Friendly Normally Off Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
2014
Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme.
IEEE J. Solid State Circuits, 2014
ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing.
Proceedings of the Symposium on VLSI Circuits, 2014
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes.
IEEE J. Solid State Circuits, 2013
2012
Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications.
IEEE J. Solid State Circuits, 2012
A 50 ns Verify Speed in Resistive Random Access Memory by Using a Write Resistance Tracking Circuit.
IEICE Trans. Electron., 2012
2011
IEEE Des. Test Comput., 2011
A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
A process for high yield and high performance carbon nanotube field effect transistors.
Microelectron. Reliab., 2010
IET Comput. Digit. Tech., 2010