Lih-Yih Chiou
Orcid: 0000-0002-4161-5787
According to our database1,
Lih-Yih Chiou
authored at least 39 papers
between 2001 and 2021.
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Bibliography
2021
An Energy-Efficient Conditional Biasing Write Assist With Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2021
A Reliable Near-Threshold Voltage SRAM-Based PUF Utilizing Weight Detection Technique.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021
2019
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
A Data-Traffic Aware Dynamic Power Management for General-Purpose Graphics Processing Units.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
2018
Highly Reliable Two-Step Charge-Pump Read Scheme for 1.5 F<sup>2</sup>/Bit Nonlinear Sub-Teraohm 0TNR Vertical ReRAM.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Temperature Gradient Exploration Method for Determining the Appropriate Number of Cells in Mesh-Based Thermal Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Methodology for developing virtual platforms from power-aware to power- and thermal-aware at electronic system level.
IET Cyper-Phys. Syst.: Theory & Appl., 2018
Single bit-line 8T SRAM cell with asynchronous dual word-line control for bit-interleaved ultra-low voltage operation.
IET Circuits Devices Syst., 2018
Proceedings of the International SoC Design Conference, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Temperature gradient-aware thermal simulator for three-dimensional integrated circuits.
IET Comput. Digit. Tech., 2017
Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
A low store energy and robust ReRAM-based flip-flop for normally off microprocessors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
Memory access algorithm for low energy CPU/GPU heterogeneous systems with hybrid DRAM/NVM memory architecture.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Proceedings of the VLSI Design, Automation and Test, 2015
2014
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
A power-efficient pulse-based in-situ timing error predictor for PVT-variation sensitive circuits.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2012
Minimum convertible voltage analysis for ratioless and robust subthreshold level conversion.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Buffer size minimization method considering mix-clock domains and discontinuous data access.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
A fast and effective dynamic trace-based method for analyzing architectural performance.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering.
J. Signal Process. Syst., 2010
A Sub-200-mV Voltage-Scalable SRAM With Tolerance of Access Failure by Self-Activated Bitline Sensing.
IEEE Trans. Circuits Syst. II Express Briefs, 2010
2009
Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics.
IEEE Trans. Very Large Scale Integr. Syst., 2009
System-Level Bus-Based Communication Architecture Exploration Using a Pseudoparallel Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
A full code-patterns coverage high-speed embedded ROM using dynamic virtual guardian technique.
IEEE J. Solid State Circuits, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
Synthesis of application-specific highly efficient multi-mode cores for embedded systems.
ACM Trans. Embed. Comput. Syst., 2005
2004
Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004
2003
Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications.
Proceedings of the 2003 Design, 2003
2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
2001
Signal Strength Based Switching Activity Modeling and Estimation for DSP Applications.
VLSI Design, 2001
Proceedings of the IEEE International Conference on Acoustics, 2001