Shyh-Shyuan Sheu

According to our database1, Shyh-Shyuan Sheu authored at least 32 papers between 2010 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors.
IEEE J. Solid State Circuits, 2020

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
NV-BNN: An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI Edge.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

Circuit Design Challenges in Computing-in-Memory for AI Edge Devices.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
Highly Reliable Two-Step Charge-Pump Read Scheme for 1.5 F<sup>2</sup>/Bit Nonlinear Sub-Teraohm 0TNR Vertical ReRAM.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

2017
A 3T1R Nonvolatile TCAM Using MLC ReRAM for Frequent-Off Instant-On Filters in IoT and Big-Data Processing.
IEEE J. Solid State Circuits, 2017

Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

2016
A ReRAM-Based 4T2R Nonvolatile TCAM Using RC-Filtered Stress-Decoupled Scheme for Frequent-OFF Instant-ON Search Engines Used in IoT and Big-Data Processing.
IEEE J. Solid State Circuits, 2016

Low-Power MCU With Embedded ReRAM Buffers as Sensor Hub for IoT Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

A low store energy and robust ReRAM-based flip-flop for normally off microprocessors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Designs of emerging memory based non-volatile TCAM for Internet-of-Things (IoT) and big-data processing: A 5T2R universal cell.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Memory access algorithm for low energy CPU/GPU heterogeneous systems with hybrid DRAM/NVM memory architecture.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Set-Triggered-Parallel-Reset Memristor Logic for High-Density Heterogeneous-Integration Friendly Normally Off Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

RRAM-based 7T1R nonvolatile SRAM with 2x reduction in store energy and 94x reduction in restore energy for frequent-off instant-on applications.
Proceedings of the Symposium on VLSI Circuits, 2015

17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme.
IEEE J. Solid State Circuits, 2014

ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing.
Proceedings of the Symposium on VLSI Circuits, 2014

A nonvolatile look-up table using ReRAM for reconfigurable logic.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

A low-power subthreshold-to-superthreshold level-shifter for sub-0.5V embedded resistive RAM (ReRAM) macro in ultra low-voltage chips.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes.
IEEE J. Solid State Circuits, 2013

2012
Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications.
IEEE J. Solid State Circuits, 2012

A 50 ns Verify Speed in Resistive Random Access Memory by Using a Write Resistance Tracking Circuit.
IEICE Trans. Electron., 2012

Endurance-aware circuit designs of nonvolatile logic and nonvolatile sram using resistive memory (memristor) device.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Fast-Write Resistive RAM (RRAM) for Embedded Applications.
IEEE Des. Test Comput., 2011

Resistance switching for RRAM applications.
Sci. China Inf. Sci., 2011

Training-based forming process for RRAM yield improvement.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Circuit design challenges in embedded memory and resistive RAM (RRAM) for mobile SoC and 3D-IC.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Challenges and trends in low-power 3D die-stacked IC designs using RAM, memristor logic, and resistive memory (ReRAM).
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Low power design of phase-change memory based on a comprehensive model.
IET Comput. Digit. Tech., 2010


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