Tzu-Kun Ku

According to our database1, Tzu-Kun Ku authored at least 14 papers between 2001 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2016
Low-Power MCU With Embedded ReRAM Buffers as Sensor Hub for IoT Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

A low store energy and robust ReRAM-based flip-flop for normally off microprocessors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Set-Triggered-Parallel-Reset Memristor Logic for High-Density Heterogeneous-Integration Friendly Normally Off Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

RRAM-based 7T1R nonvolatile SRAM with 2x reduction in store energy and 94x reduction in restore energy for frequent-off instant-on applications.
Proceedings of the Symposium on VLSI Circuits, 2015

17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Read circuits for resistive memory (ReRAM) and memristor-based nonvolatile Logics.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme.
IEEE J. Solid State Circuits, 2014

ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing.
Proceedings of the Symposium on VLSI Circuits, 2014

A nonvolatile look-up table using ReRAM for reconfigurable logic.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes.
IEEE J. Solid State Circuits, 2013

Challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2011
A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2001
Impact of interface nature on deep sub-micron Al-plug resistance.
Microelectron. Reliab., 2001


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