Tsuneaki Fuse

According to our database, Tsuneaki Fuse authored at least 4 papers between 1989 and 2003.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2003

A 0.5-V power-supply scheme for low-power system LSIs using multi-V_th SOI CMOS technology.

Tsuneaki Fuse, Masako Ohta, Motoki Tokumasu, Hiroshige Fujii, Shigeru Kawanaka, Atsushi Kameyama

IEEE J. Solid State Circuits, 2003

1993

Low-power on-chip supply voltage conversion scheme for ultrahigh-density DRAMs.

Daisaburo Takashima, Shigeyoshi Watanabe, Tsuneaki Fuse, Kazumasa Sunouchi, Takahiko Hara

IEEE J. Solid State Circuits, April, 1993

BiCMOS circuit technology for high-speed DRAMs.

Shigeyoshi Watanabe, Koji Sakui, Tsuneaki Fuse, Takahiko Hara, Seiichi Aritome, Katsuhiko Hieda

IEEE J. Solid State Circuits, January, 1993

1989

An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode.

Shigeyoshi Watanabe, Yukihito Oowaki, Yasuo Itoh, Koji Sakui, Kenji Numata, Tsuneaki Fuse, Takayuki Kobayashi, Kenji Tsuchida, Masahiko Chiba, Takahiko Hara, Masako Ohta, Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, Takeshi Hamamoto, Kazunori Ohuchi, Fujio Masuoka

IEEE J. Solid State Circuits, June, 1989