Atsushi Kameyama

According to our database1, Atsushi Kameyama authored at least 5 papers between 2002 and 2006.

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Bibliography

2006
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor.
IEEE J. Solid State Circuits, 2006

Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
The design methodology and implementation of a first-generation CELL processor: a multi-core SoC.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2003
A 0.5-V power-supply scheme for low-power system LSIs using multi-V<sub>th</sub> SOI CMOS technology.
IEEE J. Solid State Circuits, 2003

2002
A new reduced clock-swing flip-flop: NAND-type keeper flip-flop (NDKFF).
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002


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