Kazunori Ohuchi

According to our database, Kazunori Ohuchi authored at least 5 papers between 1994 and 1998.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1998

Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's.

Daisaburo Takashima, Yukihito Oowaki, Shigeyoshi Watanabe, Kazunori Ohuchi

IEEE J. Solid State Circuits, 1998

1997

A compact on-chip ECC for low cost flash memories.

Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Riichiro Shirota, Seiichi Aritome, Hiroshi Watanabe, Gertjan Hemink, Kazuhiro Shimizu, Shinji Sato, Yuji Takeuchi, Kazunori Ohuchi

IEEE J. Solid State Circuits, 1997

1994

A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory.

Tomoharu Tanaka, Yoshiyuki Tanaka, Hiroshi Nakamura, Koji Sakui, Hideko Oodaira, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka, Hisashi Hara

IEEE J. Solid State Circuits, November, 1994

Standby/active mode logic for sub-1-V operating ULSI memory.

Daisaburo Takashima, Shigeyoshi Watanabe, Hiroalu Nakano, Yukihito Oowaki, Kazunori Ohuchi, Hiroyuki Tango

IEEE J. Solid State Circuits, April, 1994

Open/folded bit-line arrangement for ultra-high-density DRAM's.

Daisaburo Takashima, Shigeyoshi Watanabe, Hiroaki Nakano, Yukihito Oowaki, Kazunori Ohuchi

IEEE J. Solid State Circuits, April, 1994