Daisaburo Takashima

According to our database1, Daisaburo Takashima authored at least 13 papers between 2006 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
A 7T-SRAM With Data-Write Technique by Capacitive Coupling.
IEEE J. Solid State Circuits, 2019

2015
Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs.
IEEE J. Solid State Circuits, 2015

2012
An Embedded DRAM Technology for High-Performance NAND Flash Memories.
IEEE J. Solid State Circuits, 2012

Session 2 overview: High-bandwidth DRAM & PRAM: Memory subcommittee.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs.
IEEE J. Solid State Circuits, 2011

A 100 MHz Ladder FeRAM Design With Capacitance-Coupled-Bitline (CCB) Cell.
IEEE J. Solid State Circuits, 2011

A 128 Mb Chain FeRAM and System Design for HDD Application and Enhanced HDD Performance.
IEEE J. Solid State Circuits, 2011

Future system and memory architectures: Transformations by technology and applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode.
IEEE Trans. Very Large Scale Integr. Syst., 2010

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes.
IEEE J. Solid State Circuits, 2010


2009

2006
A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006


  Loading...