Tsuneo Nakata

According to our database, Tsuneo Nakata authored at least 16 papers between 1994 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Data Traffic Offloading and Rate Control for Vehicles Using Radio Environment, Network Load and Route Planning.

Takeo Ohseki, Kosuke Yamazaki, Daiki Maemoto, Shigeki Kawai, Tsuneo Nakata, Akira Itou

Proceedings of the 32nd IEEE Annual International Symposium on Personal, 2021

2016

Precise Location by Fingerprinting Road Segments with Variation of Broadcast Wave Reception.

Yuji Kamiya, Toru Nagura, Shigeki Kawai, Tsuneo Nakata

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

2014

Precise Location by Fingerprinting Road Segments with Variation of Wireless Reception.

Tsuneo Nakata, Shigeki Kawai

Proceedings of the IEEE 79th Vehicular Technology Conference, 2014

2005

Integrating UML into SoC Design Process.

Qiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo Nakata

Proceedings of the 2005 Design, 2005

2004

System-on-Chip Verification Process Using UML.

Qiang Zhu, Tsuneo Nakata, Masataka Mine, Kenichiro Kuroki, Yoichi Endo, Takashi Hasegawa

Proceedings of the UML Modeling Languages and Applications, 2004

System-on-chip validation using UML and CWL.

Qiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo Nakata

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003

Multi-event algorithms and protocols for fast and robust distributed mesh provisioning and restoration.

Tsuneo Nakata

Bell Labs Tech. J., 2003

2002

Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract).

Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

An Object-Oriented Design Process for System-on-Chip Using UML.

Tsuneo Nakata, Akio Matsuda, Minoru Shoji, Shinya Kuwamura, Qiang Zhu

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

2001

A Method of Static Compaction of Test Stimuli.

Kwame Osei Boateng, Hideaki Konishi, Tsuneo Nakata

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Dataflow Analysis for Resource Contention and Register Leakage Properties.

Subir K. Roy, Hiroaki Iwashita, Tsuneo Nakata

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Formal verification based on assume and guarantee approach - a case study (short paper).

Subir K. Roy, Hiroaki Iwashita, Tsuneo Nakata

Proceedings of ASP-DAC 2000, 2000

1998

An approach to verify a large scale system-on-a-chip using symbolic model checking.

Koichiro Takayama, Taizo Satoh, Tsuneo Nakata, Fumiyasu Hirose

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1997

Forward model checking techniques oriented to buggy designs.

Hiroaki Iwashita, Tsuneo Nakata

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996

CTL model checking based on forward state traversal.

Hiroaki Iwashita, Tsuneo Nakata, Fumiyasu Hirose

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1994

Automatic test program generation for pipelined processors.

Hiroaki Iwashita, Satoshi Kowatari, Tsuneo Nakata, Fumiyasu Hirose

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994