Fumiyasu Hirose

According to our database, Fumiyasu Hirose authored at least 16 papers between 1980 and 1999.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

1999

Speeding Up Look-up-Table Driven Logic Simulation.

Rajeev Murgai, Fumiyasu Hirose, Masahiro Fujita

Proceedings of the VLSI: Systems on a Chip, 1999

1998

An approach to verify a large scale system-on-a-chip using symbolic model checking.

Koichiro Takayama, Taizo Satoh, Tsuneo Nakata, Fumiyasu Hirose

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1997

Acceleration of behavioral simulation on simulation specific machines.

Minoru Shoji, Fumiyasu Hirose, Shintaro Shimogori, Satoshi Kowatari, Hiroshi Nagai

Proceedings of the European Design and Test Conference, 1997

Acceleration of mincut partitioning using hardware CAD accelerator TP5000.

Masahiro Sano, Shintaro Shimogori, Fumiyasu Hirose

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

CTL model checking based on forward state traversal.

Hiroaki Iwashita, Tsuneo Nakata, Fumiyasu Hirose

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995

Logic synthesis for a single large look-up table.

Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Panel: New Research Problems in the Emerging Test Technology.

Vishwani D. Agrawal, Bernard Courtois, Fumiyasu Hirose, Sandip Kundu, Chung-Len Lee, Yinghua Min, Parimal Pal Chaudhuri

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994

Automatic test program generation for pipelined processors.

Hiroaki Iwashita, Satoshi Kowatari, Tsuneo Nakata, Fumiyasu Hirose

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1992

Test pattern generation system for delay faults using a high speed simulation processor 'SP'.

Yukiko Izuta, Fumiyasu Hirose

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Performance Evaluation of an Event-Driven Logic Simulation Machine.

Fumiyasu Hirose

Proceedings of the 29th Design Automation Conference, 1992

1990

A high-speed test-generation method using a test generation circuit.

Fumiyasu Hirose, Koichiro Takayama, Nobuaki Kawato

Syst. Comput. Jpn., 1990

1989

Simulation processor "SP".

Hiroshi Yamada, Fumiyasu Hirose, Junichi Niitsuma, Tatsuya Shindo

Syst. Comput. Jpn., 1989

Logic simulation engines in Japan.

Shigeru Takasaki, Fumiyasu Hirose, Akihiko Yamada

IEEE Des. Test, 1989

1988

A Method to Generate Tests for Combinational Logic Circuits Using an Ultra-High-Speed Logic Simulator.

Fumiyasu Hirose, Koichiro Takayama, Nobuaki Kawato

Proceedings of the Proceedings International Test Conference 1988, 1988

Logic Simulation System Using Simulation Processor (SP).

Minoru Saitoh, Kenji Iwata, Akiko Nokamura, Makoto Kakegawa, Junichi Masuda, Hirofumi Hamamura, Fumiyasu Hirose, Nobuaki Kawato

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1980

Efficient placement and routing techniques for master slice LSI.

Hiroshi Shiraishi, Fumiyasu Hirose

Proceedings of the 17th Design Automation Conference, 1980