Kwame Osei Boateng

According to our database1, Kwame Osei Boateng authored at least 14 papers between 1997 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
PSTRM: Privacy-aware sociopsychological trust and reputation model for wireless sensor networks.
Peer-to-Peer Netw. Appl., 2020

2018
The adoption of socio- and bio-inspired algorithms for trust models in wireless sensor networks: A survey.
Int. J. Commun. Syst., 2018

2017
Tamper-aware authentication framework for wireless sensor networks.
IET Wirel. Sens. Syst., 2017

2015
A Retrofit Design Science Methodology for Smart Metering Design in Developing Countries.
Proceedings of the 15th International Conference on Computational Science and Its Applications, 2015

2013
Small-Scale Fading Characteristics in Cellular Networks in Ghana.
Int. J. Interdiscip. Telecommun. Netw., 2013

2003
BIST-Aided Scan Test - A New Method for Test Cost Reduction.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

2002
On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

2001
A Method of Static Compaction of Test Stimuli.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
General BIST-Amenable Method of Test Generation for Iterative Logic Arrays.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

1999
A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Multiple Fault Diagnosis in Logic Circuits Using EB Tester and Multiple/Single Fault Simulators.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998
Diagnosis of Single Gate Delay Faults in Combinational Circuits using Delay Fault Simulation.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

Design of C-Testable Multipliers Based on the Modified Booth Algorithm.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997


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