Sreeranga P. Rajan

According to our database1, Sreeranga P. Rajan authored at least 32 papers between 1992 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Evaluation of Transfer Learning for Adverse Drug Event (ADE) and Medication Entity Extraction.
Proceedings of the 3rd Clinical Natural Language Processing Workshop, 2020

Automatic Assessment Item Bank Calibration for Learning Gap Identification.
Proceedings of the 2018 International Conference on Advances in Computing, 2018

KLOVER: Automatic Test Generation for C and C Programs, Using Symbolic Execution.
IEEE Softw., 2017

Enhancement of Data Level Security in MongoDB.
Proceedings of the Intelligent Distributed Computing, 2014

Big Data Analytics for Security.
IEEE Secur. Priv., 2013

GKLEE: concolic verification and test generation for GPUs.
Proceedings of the 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2012

Automated System Testing of Dynamic Web Applications.
Proceedings of the Software and Data Technologies - 6th International Conference, 2011

Client-tier Validation of Dynamic Web Applications.
Proceedings of the ICSOFT 2011, 2011

Automated Driver Generation for Analysis of Web Applications.
Proceedings of the Fundamental Approaches to Software Engineering, 2011

KLOVER: A Symbolic Execution and Automatic Test Generation Tool for C++ Programs.
Proceedings of the Computer Aided Verification - 23rd International Conference, 2011

WEAVE: WEb Applications Validation Environment.
Proceedings of the 31st International Conference on Software Engineering, 2009

Context-Sensitive Relevancy Analysis for Efficient Symbolic Execution.
Proceedings of the Programming Languages and Systems, 6th Asian Symposium, 2008

Combining environment generation and slicing for modular software model checking.
Proceedings of the 22nd IEEE/ACM International Conference on Automated Software Engineering (ASE 2007), 2007

Embedded Software Verification Using Symbolic Execution and Uninterpreted Functions.
Int. J. Parallel Program., 2006

Error Detection in Concurrent Java Programs.
Electron. Notes Theor. Comput. Sci., 2006

Application of automated environment generation to commercial software.
Proceedings of the ACM/SIGSOFT International Symposium on Software Testing and Analysis, 2006

ACM Trans. Storage, 2005

High level hardware validation using hierarchical message sequence charts.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Program slicing for VHDL.
Int. J. Softw. Tools Technol. Transf., 2002

Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract).
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Automatic formal verification of DSP software.
Proceedings of the 37th Conference on Design Automation, 2000

Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

Program Slicing of Hardware Description Languages.
Proceedings of the Correct Hardware Design and Verification Methods, 1999

Model Checking Based on Sequential ATPG.
Proceedings of the Computer Aided Verification, 11th International Conference, 1999

ATM switch design by high-level modeling, formal verification and high-level synthesis.
ACM Trans. Design Autom. Electr. Syst., 1998

Integration of High-Level Modeling, Formal Verification, and High-Level Synthesis in ATM Switch Design.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Two Real Formal Verification Experiences: ATM Switch Chip and Parallel Cache Protocol.
Proceedings of the Applied Formal Methods, 1998

ATM Switch Design: Parametric High-Level Modeling and Formal Verification.
Proceedings of the Algebraic Methodology and Software Technology, 1997

From VHDL to efficient and first-time-right designs: a formal approach.
ACM Trans. Design Autom. Electr. Syst., 1996

From Abstract Data Types to Shift Registers: A Case Study in Formal Specification and Verification at Differing Levels of Abstraction using Theorem Proving and Symbolic Simulation.
Proceedings of the Higher Order Logic Theorem Proving and its Applications, 1993

Executing HOL Specifications: Towards an Evaluation Semantics for Classical Higher Order Logic.
Proceedings of the Higher Order Logic Theorem Proving and its Applications, 1992